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Challenges and Opportunities for Ultra- Low Power Design for Quantum Computing Applications

Sudipto Chakraborty

Published Jan 26, 2026• 0 citations
Publisher

Abstract

This chapter will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76×10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.

DOI
10.1201/9788743807087-6

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This chapter will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76×10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.
A scalable, non-multiplexed cryogenic 14-nm FinFET quantum bit (qubit) state controller (QSC) for use in the semi-autonomous control of superconducting transmon qubits is reported. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low-power current-mode single sideband upconversionI/Q{I}/{Q}I/Qmixer-based RF arbitrary waveform generator (AWG). Implemented in the 14-nm CMOS FinFET technology, the QSC generates control signals in its target 4.5–5.5-GHz-frequency range, achieving an spurious free dynamic range (SFDR) > 50 dB for a signal bandwidth of 500 MHz. With the controller operating in the 4 K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmonT1T_{1}T1​andT2T_{2}T2​coherence times were 75.7 and 73μs\mu \text{s}μs, respectively, in each case comparable to results achieved using conventional room temperature (RT) controls. In further tests with transmons, a qubit-limited error rate of 7.76 × 10−4 per Clifford gate is achieved, again comparable to the results achieved using RT controls. The QSC’s maximum RF output power is −18 dBm, and power dissipation per qubit under active control is 23 mW.
This article will review recent progress in cryogenic CMOS designs for future scaled quantum computing applications. After introducing the scaling challenges associated with qubit control and readout electronics operating at room temperature, approaches taken to date to cryogenic control electronics design will be discussed, focusing on the most recent relevant publications. Elements of ultra-low power circuit and system design approaches for cryogenic controllers in scaled CMOS nodes (40nm to 14nm) will be reviewed, including a discussion of current state-of-the art cryogenic controller performance and power efficiency. Note that leading designs, when operated as transmon qubit state controllers, have achieved gate error rates in the range of 10-4 to 10-3 achieving spurious free dynamic range (SFDR) of ~40dB while consuming 4-23mW of power per qubit under active control, with power efficiency strongly driven by the complexity of the digital processor integrated in the controller design. These demonstrations, while significant, are just the first steps toward achieving the performance, efficiency, and scalability that will be required for future systems. This review article will discuss fundamental tradeoffs in CMOS cryogenic designs in order to address the needs of future scaled quantum computing systems.
Today’s quantum computing systems rely on commercial electronics operating at room temperature in order to perform control and readout operations for qubits [1] –[6]. The qubits operate at cryogenic temperatures; the signals that support control and readout of qubits therefore traverse multiple temperature stages in a dilution refrigerator to enable interaction with the qubits of a quantum computer. For many of the most advanced quantum computers built to date, the control of each individual qubit demands application of a radiofrequency pulse that is precisely calibrated in frequency, amplitude, and phase. Oubit readout demands the amplification of very low amplitude signals that are then post-processed to categorize the state of the qubit being measured. Oubit control electronics are implemented using arbitrary waveform generators (AWGs) of various types. The scalability of such systems is challenged by the need to scale the number of qubit control electronics units linearly with the number of qubits in the system. One approach to mitigating this challenge that is under active exploration is the use of multi-channel AWGs (tailored to the requirements of qubit control) that operate at the 4K stage of a quantum computing system [7] –[10]. Oubit readout electronics are typically implemented using multiple stages of amplification and then DSP-based readout performed at room temperature. In today’s systems, while readout electronics benefits from multiplexing of the readout signals (enabling a single cascade of moderately wideband amplifiers to support the delivery of multiple readout signals to the room-temperature electronics), again, the scalability of this approach is challenged much as is the case with control electronics. One approach to mitigating the readout challenge is the expanded use of cryogenic electronics in the readout chain. Success in the implementation of cryogenic control and readout solutions depends critically on multiple CMOS sub-components; in this paper we focus on SRAM and low noise amplifiers (LNAs). Note that SRAM is critical for both control and readout applications as a mixed-signal solution involving the combination of a custom processor and analog elements is highly desirable in both cases. Further, while the LNA is directly used as an element in the readout chain, a deep assessment of LNA performance and opportunities strongly benefits overall understanding of achievable noise performance in CMOS technologies at cryogenic temperatures and is therefore impoitant in both control and readout contexts.
Abstract Qubit control electronics composed of CMOS circuits are of critical interest for next generation quantum computing systems. A CMOS–based application specific integrated circuit (ASIC) fabricated in 14nm FinFET technology was used to generate and sequence qubit control waveforms and demonstrate a two–qubit cross resonance gate between fixed frequency transmons. The controller was thermally anchored to the T = 4K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single–side banded output frequencies between 4.5 and 5.5 GHz with a maximum power output of -18 dBm. Randomized benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single–qubit gates, and 17.51 IPC for two–qubit gates. A single–qubit error per gate of є1Q=8e-4 and two–qubit error per gate of є2Q=1.4e-2 is shown. A drive–induced Z–rotation is observed by way of a rotary echo experiment; this observation is consistent with expected qubit behavior given measured excess local oscillator (LO) leakage from the CMOS chip. The effect of spurious drive induced Z–errors is numerically evaluated with a two–qubit model Hamiltonian, and shown to be in good agreement with measured RB data. The modeling results suggest the Z–error varies linearly with pulse amplitude.
Qubit control electronics composed of CMOS circuits are of critical interest for next generation quantum computing systems. A CMOS-based application specific integrated circuit (ASIC) fabricated in 14nm FinFET technology was used to generate and sequence qubit control waveforms and demonstrate a two-qubit cross resonance gate between fixed frequency transmons. The controller was thermally anchored to the T = 4K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single--side banded output frequencies between 4.5 and 5.5 GHz with a maximum power output of -18 dBm. Randomized benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single-qubit gates, and 17.51 IPC for two-qubit gates. A single-qubit error per gate of ε1Qε_{\text{1Q}}ε1Q​=8e-4 and two-qubit error per gate of ε2Qε_\text{2Q}ε2Q​=1.4e-2 is shown. A drive-induced Z-rotation is observed by way of a rotary echo experiment; this observation is consistent with expected qubit behavior given measured excess local oscillator (LO) leakage from the CMOS chip. The effect of spurious drive induced Z-errors is numerically evaluated with a two-qubit model Hamiltonian, and shown to be in good agreement with measured RB data. The modeling results suggest the Z-error varies linearly with pulse amplitude.
Error-corrected quantum computing is expected to require at least 105to 106physical qubits. Superconducting transmons, which are promising qubit candidates for scaled quantum computing systems, typically require individually tailored RF pulses in the 4-to-6 GHz range to manipulate their states, so scaling to 106qubits presents an enormous challenge. Providing a control line for every qubit from room temperature (RT) to the 10mK environment does not appear to be viable for a 106qubit system due to multiple factors, including RF loss, mechanical congestion, heat load, and connector unreliability. TDM cannot be used to reduce the number of control lines since all of the qubits may need to be activated at once (e.g., during quantum error correction (QEC) cycles). FDM has been proposed but is undesirable because extra tones can give rise to unwanted qubit excitations.