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IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS)

Efficient Clocking Strategies for Adiabatic Quantum-Flux-Parametron 8-bit Ripple Carry Adder Implementation

M. Dharani, Dudekonda Upendra, Bathula Surendra Babu, Bingi Sathwika, Chinnepalli Harika

Published Jun 28, 2024• 1 citation
Publisher

Abstract

The implementation of an Adiabatic Quantum-Flux-Parametron (AQFP) 8-bit Ripple Carry Adder with the capability to operate indifferent clock cycles is explored in this study. Leveraging Superconducting digital circuits employing Josephson junctions, this approach garners significant attention due to its ultra-fast operation and minimal energy consumption. In this study, we investigate the implementation of an Adiabatic Quantum-Flux-Parametron (AQFP) 8-bit Ripple Carry Adder with the flexibility to operate across different clock cycles. Leveraging the capabilities of Superconducting digital circuits and Josephson junctions, this approach is notable for its rapid operation and minimal energy consumption. Our focus lies on examining the effects of varying clock cycles on key performance parameters. A comprehensive analysis of memory usage, CPU utilization, and execution time is presented for different phase delays corresponding to 1 clock cycle, 2 clock cycles, both 1 and 2 clock cycles, and no clock cycle. The results indicate subtle fluctuations in memory usage, CPU utilization, and execution time across these configurations, providing insights into the system's adaptability to different clocking schemes. Furthermore, we propose a novel clocking strategy tailored specifically for AQFP circuits, termed as “indifferent clock cycles,” which allows for seamless operation irrespective of the clock cycle duration. Through this approach, we aim to optimize system performance while accommodating diverse operational requirements. By exploring the implications of indifferent clock cycles on AQFP-based systems, we aim to pave the way for more versatile and efficient superconducting digital circuits. This research contributes to the ongoing efforts in advancing the field of quantum-flux-parametron logic and its applications in high-performance computing systems.

DOI
10.1109/iciteics61368.2024.10625097

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The implementation of an Adiabatic Quantum-Flux-Parametron (AQFP) 8-bit Ripple Carry Adder with the capability to operate indifferent clock cycles is explored in this study. Leveraging Superconducting digital circuits employing Josephson junctions, this approach garners significant attention due to its ultra-fast operation and minimal energy consumption. In this study, we investigate the implementation of an Adiabatic Quantum-Flux-Parametron (AQFP) 8-bit Ripple Carry Adder with the flexibility to operate across different clock cycles. Leveraging the capabilities of Superconducting digital circuits and Josephson junctions, this approach is notable for its rapid operation and minimal energy consumption. Our focus lies on examining the effects of varying clock cycles on key performance parameters. A comprehensive analysis of memory usage, CPU utilization, and execution time is presented for different phase delays corresponding to 1 clock cycle, 2 clock cycles, both 1 and 2 clock cycles, and no clock cycle. The results indicate subtle fluctuations in memory usage, CPU utilization, and execution time across these configurations, providing insights into the system's adaptability to different clocking schemes. Furthermore, we propose a novel clocking strategy tailored specifically for AQFP circuits, termed as “indifferent clock cycles,” which allows for seamless operation irrespective of the clock cycle duration. Through this approach, we aim to optimize system performance while accommodating diverse operational requirements. By exploring the implications of indifferent clock cycles on AQFP-based systems, we aim to pave the way for more versatile and efficient superconducting digital circuits. This research contributes to the ongoing efforts in advancing the field of quantum-flux-parametron logic and its applications in high-performance computing systems.
Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family that can operate with low switching energy due to adiabatic switching. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current. We demonstrated several AQFP logic gates with delay-line clocking and demonstrated a phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. In the present study, we design and demonstrate an AQFP 8-bit ripple carry adder with delay-line clocking to show that delay-line clocking and the phase skipping operation are applicable to large-scale AQFP circuits. The latency of this adder is 960 ps, which is 40% of that for a conventional design. Moreover, due to the phase skipping operation, the junction count is reduced to approximately 70% of that for the conventional design. We find that this adder can operate at up to 4 GHz. The above results indicate that large-scale AQFP circuits can operate with low latency and low junction count by using delay-line clocking and a phase skipping operation.
Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. In this paper, we conducted the high-frequency operation and energy measurement of an AQFP circuit with more than 1000 Josephson junctions in the experiment. We designed an 8-bit carry look-ahead adder (CLA) using AQFP gates and fabricated it using an advanced fabrication technology, the AIST 10 kA/cm2 Nb high-speed standard process. The correct operation of the 8-bit CLA was demonstrated at a 1-GHz clock frequency for a critical carry propagation test vector. The energy dissipation of the 8-bit CLA was measured by observing the power of excitation current. Our results showed that the energy dissipation per operation of the 8-bit CLA can be estimated to be approximately 1.5 aJ, or 24kBT per junction, where kB is the Boltzmann constant and T is the operating temperature.
An adiabatic quantum flux parametron (AQFP) is a two-terminal superconducting device capable of amplifying or inverting digital input signals at near-kT energy dissipation. This ultra-low power device is desirable for myriad reasons, including high performance accelerator applications as CMOS processors become more and more limited by energy consumption. Promising performance results have been realized on AQFP processors; however, scaling these results to larger computing systems faces engineering challenges due to device density and power distribution. AQFP circuits require a multi-phase activation signal to propagate logic. If data is not properly aligned with the activation phase, it can be dropped or shifted to an incorrect phase and disrupt circuit operation. This work presents design and simulation of an activation phase synchronizer: a simple circuit that will accept data arriving on any phase and re-align it to a known phase of the subsequent cycle. The phase synchronizer can be useful for mitigating clock skew across clock domains or play an important role in asynchronous design where the arrival time of data may be unknown.
Adiabatic quantum-flux-parametron (AQFP) circuits are very low-power due to zero static power consumption and adiabatic switching operations. However, compared to other superconducting circuits, such as rapid single-flux-quantum logic, the operation frequency is relatively low and the latency is relatively large. In this work, we propose multi-excitation AQFP (ME-AQFP) circuits for high-speed and low-latency operations. In ME-AQFP, the intrinsic periodicity of the potential energy of a Josephson device with respect to applied magnetic fluxes is utilized to multiply operation frequencies and reduce latency. In a numerical simulation, we demonstrated an ME-AQFP AND gate, which operates at 10 GHz or 20 GHz with 5-GHz excitation currents. We also evaluated the energy efficiency of ME-AQFP circuits. In an experiment, we successfully demonstrated an ME-AQFP XOR gate and an ME-AQFP full adder.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments. We also demonstrate that delay-line clocking enables phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. The results indicate that delay-line clocking can enable low-latency, low-energy, large-scale AQFP circuits.
We have been investigating an ultra-low-power adiabatic quantum-flux-parametron (AQFP) logic, the energy dissipation of which can be decreased by changing its potential energy slowly or adiabatically. In the present study, we designed basic AQFP logic gates and an AQFP 1-bit full adder, and examined their operations through simulations and experiments. The AQFP 1-bit full adder is composed of 46 Josephson junctions, which is approximately one-quarter the number of junctions of a full adder using conventional rapid single-flux-quantum logic. The measurement results indicated that the AQFP 1-bit full adder has a wide current bias margin of as large as ±27.8%.