An adiabatic quantum flux parametron (AQFP) is a two-terminal superconducting device capable of amplifying or inverting digital input signals at near-kT energy dissipation. This ultra-low power device is desirable for myriad reasons, including high performance accelerator applications as CMOS processors become more and more limited by energy consumption. Promising performance results have been realized on AQFP processors; however, scaling these results to larger computing systems faces engineering challenges due to device density and power distribution. AQFP circuits require a multi-phase activation signal to propagate logic. If data is not properly aligned with the activation phase, it can be dropped or shifted to an incorrect phase and disrupt circuit operation. This work presents design and simulation of an activation phase synchronizer: a simple circuit that will accept data arriving on any phase and re-align it to a known phase of the subsequent cycle. The phase synchronizer can be useful for mitigating clock skew across clock domains or play an important role in asynchronous design where the arrival time of data may be unknown.
An adiabatic quantum flux parametron (AQFP) is a two-terminal superconducting device capable of amplifying or inverting digital input signals at near-kT energy dissipation. This ultra-low power device is desirable for myriad reasons, including high performance accelerator applications as CMOS processors become more and more limited by energy consumption. Promising performance results have been realized on AQFP processors; however, scaling these results to larger computing systems faces engineering challenges due to device density and power distribution. AQFP circuits require a multi-phase activation signal to propagate logic. If data is not properly aligned with the activation phase, it can be dropped or shifted to an incorrect phase and disrupt circuit operation. This work presents design and simulation of an activation phase synchronizer: a simple circuit that will accept data arriving on any phase and re-align it to a known phase of the subsequent cycle. The phase synchronizer can be useful for mitigating clock skew across clock domains or play an important role in asynchronous design where the arrival time of data may be unknown.
Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family that can operate with low switching energy due to adiabatic switching. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current. We demonstrated several AQFP logic gates with delay-line clocking and demonstrated a phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. In the present study, we design and demonstrate an AQFP 8-bit ripple carry adder with delay-line clocking to show that delay-line clocking and the phase skipping operation are applicable to large-scale AQFP circuits. The latency of this adder is 960 ps, which is 40% of that for a conventional design. Moreover, due to the phase skipping operation, the junction count is reduced to approximately 70% of that for the conventional design. We find that this adder can operate at up to 4 GHz. The above results indicate that large-scale AQFP circuits can operate with low latency and low junction count by using delay-line clocking and a phase skipping operation.
Adiabatic quantum-flux-parametron (AQFP) logic is a highly energy-efficient superconductor logic family. Traditionally, AQFP circuits have relied on the four-phase clocking scheme, which uses a pair of ac current sources with a 90° phase difference. The operation of each logic gate thus takes a quarter clock cycle, leading to a relatively long latency for some applications. In this Letter, we propose a low-latency clocking scheme for AQFP logic based on microwave power dividers (PDs). The whole circuit is powered by a single excitation current, which is equally split for each logic stage by a serial-type PD. As a result, the latency between adjacent logic stages is determined by the transmission line length (propagation delay) inside the PD, which can be much shorter than a quarter clock cycle. Note that the low-latency performance is independent of the horizontal length of the AQFP circuit, and thus, the proposed clocking scheme is applicable to large-scale designs where a large number of gates are horizontally placed in a single stage. For validation, several numerical simulations are conducted and a six-stage AQFP test circuit is demonstrated using the proposed power-dividing clocking scheme (with a designed latency of 20 ps per gate) at a temperature of 4.2 K.
Abstract The adiabatic quantum-flux-parametron (AQFP), which can operate with ultra-low energy consumption, has attracted attention as an alternative to semiconductor circuits. The development of reconfigurable AQFP devices is essential for advancing AQFP integrated circuits. However, research on reconfigurable devices at the logic gate level remains limited. We propose an AQFP circuit capable of reconfiguring its logic function by controlling the superconducting phase shift through externally applied magnetic flux. In AQFP logic, logic ‘1’ and ‘0’ are represented by the polarity of the current. The proposed circuit can switch between the Buffer function, which propagates the input current with its polarity unchanged, and the NOT function, which propagates it with the polarity inverted. We analytically derived the parameter conditions for correct operation and determined the parameters within this range to achieve adiabatic operation and sufficient element margins for experimental demonstration. We fabricated the proposed reconfigurable circuit using the 10 kA cm −2 Nb four-layer superconducting circuit fabrication process, and experimentally confirmed correct operation for both the Buffer and NOT functions. The control current margins, which are responsible for the functional reconfiguration, were −2.3% to +31.2% for chip 1 and +0.8% to +35.1% for chip 2. Both margins had widths comparable to the simulation result. This work presents the first experimental demonstration of an AQFP circuit whose function can be reconfigured using only a control current. We believe this work will contribute to the advancement of reconfigurable AQFP devices.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments. We also demonstrate that delay-line clocking enables phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. The results indicate that delay-line clocking can enable low-latency, low-energy, large-scale AQFP circuits.
Adiabatic Quantum-Flux-Parametron (AQFP) logic is a promising emerging device technology with six orders of magnitude lower power than CMOS. However, AQFP is challenged by the fact that every gate must be clocked, where proper data transfer requires connected gates to have shifted but overlapping clocks. As a result, buffers need to be used to balance re-convergent logic paths, a problem that is exacerbated by every multi-node fanout needing a tree of clocked splitters. Recent AQFP circuit design techniques have offered an opportunity to reduce buffer costs by supporting a notion of phase-skipping but the EDA support for these advanced circuits is limited. This paper proposes the first algorithm to optimize buffer and splitter insertion for phase-skipping AQFP circuits and achieves over 31\% savings over existing buffer reduction schemes and up to 74\% savings in buffers and splitter costs over the SOTA non-phase skipping circuits.
Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient, high- performance information processing systems because it has significantly low power consumption due to the adiabatic switching of Josephson junctions. We are developing a high-performance field-programmable gate array (FPGA) using superconducting AQFP circuits to reduce its energy consumption. The all-AQFP FPGA consists of logic blocks, switch blocks, connection blocks, and memory using AQFP circuits. In particular, the memory is composed of AQFP buffer chains, enabling high-density and low-power memory. The switch blocks can perform data routing as well as several logic functions, including majority,and, andorfunctions, which increases the design flexibility of the all-AQFP FPGA. We fabricated a one-unit all-AQFP FPGA and demonstrated its reconfigurable operation at low speed. It was found that much lower power consumption can be achieved in the new FPGA than in the other superconducting FPGAs.