Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family that can operate with low switching energy due to adiabatic switching. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current. We demonstrated several AQFP logic gates with delay-line clocking and demonstrated a phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. In the present study, we design and demonstrate an AQFP 8-bit ripple carry adder with delay-line clocking to show that delay-line clocking and the phase skipping operation are applicable to large-scale AQFP circuits. The latency of this adder is 960 ps, which is 40% of that for a conventional design. Moreover, due to the phase skipping operation, the junction count is reduced to approximately 70% of that for the conventional design. We find that this adder can operate at up to 4 GHz. The above results indicate that large-scale AQFP circuits can operate with low latency and low junction count by using delay-line clocking and a phase skipping operation.
Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family that can operate with low switching energy due to adiabatic switching. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current. We demonstrated several AQFP logic gates with delay-line clocking and demonstrated a phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. In the present study, we design and demonstrate an AQFP 8-bit ripple carry adder with delay-line clocking to show that delay-line clocking and the phase skipping operation are applicable to large-scale AQFP circuits. The latency of this adder is 960 ps, which is 40% of that for a conventional design. Moreover, due to the phase skipping operation, the junction count is reduced to approximately 70% of that for the conventional design. We find that this adder can operate at up to 4 GHz. The above results indicate that large-scale AQFP circuits can operate with low latency and low junction count by using delay-line clocking and a phase skipping operation.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments. We also demonstrate that delay-line clocking enables phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. The results indicate that delay-line clocking can enable low-latency, low-energy, large-scale AQFP circuits.
Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching. However, AQFP logic has somewhat long latency due to the multiphase clocking scheme, in which each logic operation requires a quarter clock cycle. The latency in AQFP logic should be improved in order to design complex digital circuits such as microprocessors. In the present paper, we propose a low-latency clocking scheme for AQFP logic, which we call delay-line clocking. In delay-line clocking, the latency for each logic operation is determined by the propagation delay of the excitation current, which can be much shorter than a quarter clock cycle. Our numerical simulation shows that AQFP gates can operate with a latency of only a few picoseconds. We fabricated an AQFP circuit adopting delay-line clocking using the 10 kA/cm2 Nb high-speed standard process provided by the National Institute of Advanced Industrial Science and Technology. The circuit was demonstrated at 4 GHz with a latency of 10 ps per gate. The above results indicate that delay-line clocking can significantly reduce the latency in AQFP logic.
Adiabatic quantum-flux-parametron (AQFP) logic is a highly energy-efficient superconductor logic family. Traditionally, AQFP circuits have relied on the four-phase clocking scheme, which uses a pair of ac current sources with a 90° phase difference. The operation of each logic gate thus takes a quarter clock cycle, leading to a relatively long latency for some applications. In this Letter, we propose a low-latency clocking scheme for AQFP logic based on microwave power dividers (PDs). The whole circuit is powered by a single excitation current, which is equally split for each logic stage by a serial-type PD. As a result, the latency between adjacent logic stages is determined by the transmission line length (propagation delay) inside the PD, which can be much shorter than a quarter clock cycle. Note that the low-latency performance is independent of the horizontal length of the AQFP circuit, and thus, the proposed clocking scheme is applicable to large-scale designs where a large number of gates are horizontally placed in a single stage. For validation, several numerical simulations are conducted and a six-stage AQFP test circuit is demonstrated using the proposed power-dividing clocking scheme (with a designed latency of 20 ps per gate) at a temperature of 4.2 K.
The implementation of an Adiabatic Quantum-Flux-Parametron (AQFP) 8-bit Ripple Carry Adder with the capability to operate indifferent clock cycles is explored in this study. Leveraging Superconducting digital circuits employing Josephson junctions, this approach garners significant attention due to its ultra-fast operation and minimal energy consumption. In this study, we investigate the implementation of an Adiabatic Quantum-Flux-Parametron (AQFP) 8-bit Ripple Carry Adder with the flexibility to operate across different clock cycles. Leveraging the capabilities of Superconducting digital circuits and Josephson junctions, this approach is notable for its rapid operation and minimal energy consumption. Our focus lies on examining the effects of varying clock cycles on key performance parameters. A comprehensive analysis of memory usage, CPU utilization, and execution time is presented for different phase delays corresponding to 1 clock cycle, 2 clock cycles, both 1 and 2 clock cycles, and no clock cycle. The results indicate subtle fluctuations in memory usage, CPU utilization, and execution time across these configurations, providing insights into the system's adaptability to different clocking schemes. Furthermore, we propose a novel clocking strategy tailored specifically for AQFP circuits, termed as “indifferent clock cycles,” which allows for seamless operation irrespective of the clock cycle duration. Through this approach, we aim to optimize system performance while accommodating diverse operational requirements. By exploring the implications of indifferent clock cycles on AQFP-based systems, we aim to pave the way for more versatile and efficient superconducting digital circuits. This research contributes to the ongoing efforts in advancing the field of quantum-flux-parametron logic and its applications in high-performance computing systems.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic stands as an energy-efficient superconductor logic family relying on ac excitations. Though a four-phase clocking scheme has been commonly applied to excite and clock AQFP circuits, the cost of multiple sources and long between-stage latency (a quarter clock cycle) remain unsatisfactory. These drawbacks are more severe for sequential logics, where feedback loops require both down-flow and reverse-flow AQFP gates, necessitating extra buffers and imposing a limit on operating depth at the same time. To overcome these restrictions, in this paper, we introduce a novel mixed clocking scheme for low-latency AQFP logic circuits allowing feedback loops. In particular, the down-flow part of the AQFP circuit is excited by an ac current through delay-lines, which can reduce the latency from input to output stages. Meanwhile, the reverse-flow part is clocked by 2 other ac currents with 90° phase difference to reduce the buffering gates. The proposed clocking scheme is first applied to a fundamental logic circuit, confirming correct functionality and low-latency operations for diverse feedback conditions. For experimental validation, we design and fabricate a 3-bit AQFP counter using the proposed clocking scheme based on an on-chip clock splitter. The circuit is examined at 4 GHz under 4.2 K temperature, where we obtain desired operations and wide excitation margins.
Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. In this paper, we conducted the high-frequency operation and energy measurement of an AQFP circuit with more than 1000 Josephson junctions in the experiment. We designed an 8-bit carry look-ahead adder (CLA) using AQFP gates and fabricated it using an advanced fabrication technology, the AIST 10 kA/cm2 Nb high-speed standard process. The correct operation of the 8-bit CLA was demonstrated at a 1-GHz clock frequency for a critical carry propagation test vector. The energy dissipation of the 8-bit CLA was measured by observing the power of excitation current. Our results showed that the energy dissipation per operation of the 8-bit CLA can be estimated to be approximately 1.5 aJ, or 24kBT per junction, where kB is the Boltzmann constant and T is the operating temperature.