Enabling 300 mm Wafer-Scale Fabrication of Superconducting Quantum Devices
Ekta Bhatia, Hunter Frost, Nicholas Pieniazek, Jakub Nalaskowski, John Mucci, Wenli Z. Collison, Brian Martinick, Geevanie Telhu, Bryan Egan, Stephen Olson, Pui Yee Hung, Ilyssa Wells, Corbet S. Johnson, Thomas Murray, Kevin Musick, Satyavolu S. Papa Rao
Superconducting quantum computing has demonstrated exponential improvements in coherence times over the past two decades, bringing us to the present Noisy Intermediate Scale Quantum (NISQ) era. Improvements in materials and fabrication techniques are still required along with circuit and algorithm innovations to move beyond the NISQ era. We discuss several aspects of the process development work that enables the fabrication of superconducting quantum devices and circuits at 300 mm wafer scale, using materials, processes and tools that are entirely compatible with high-volume integrated circuit fabs. Damascene structures of superconducting tantalum and aluminum (embedded in high resistivity silicon substrates) are described along with examples of process control. The use of such structures for coplanar waveguide resonators in quantum circuits is described, along with modifications to enable integration of normal metal traps to mitigate quasiparticle poisoning. This paper also includes a description of the considerable process development required to enable ALD-TaN based Josephson junctions fabricated with entirely 300 mm compatible processes, in contrast to the lift-off based processes currently in wide use for qubit fabrication. It concludes with a description of how these efforts help with establishing a Quantum Foundry at NY CREATES (a non-profit organization) that can democratize access to advanced qubit fabrication by offering an open superconducting quantum Process Design Kit (PDK).
Superconducting quantum computing has demonstrated exponential improvements in coherence times over the past two decades, bringing us to the present Noisy Intermediate Scale Quantum (NISQ) era. Improvements in materials and fabrication techniques are still required along with circuit and algorithm innovations to move beyond the NISQ era. We discuss several aspects of the process development work that enables the fabrication of superconducting quantum devices and circuits at 300 mm wafer scale, using materials, processes and tools that are entirely compatible with high-volume integrated circuit fabs. Damascene structures of superconducting tantalum and aluminum (embedded in high resistivity silicon substrates) are described along with examples of process control. The use of such structures for coplanar waveguide resonators in quantum circuits is described, along with modifications to enable integration of normal metal traps to mitigate quasiparticle poisoning. This paper also includes a description of the considerable process development required to enable ALD-TaN based Josephson junctions fabricated with entirely 300 mm compatible processes, in contrast to the lift-off based processes currently in wide use for qubit fabrication. It concludes with a description of how these efforts help with establishing a Quantum Foundry at NY CREATES (a non-profit organization) that can democratize access to advanced qubit fabrication by offering an open superconducting quantum Process Design Kit (PDK).
Ongoing research at SUNY Polytechnic Institute to enable large scale fabrication of quantum devices with tightly controlled performance characteristics will be presented. Josephson junctions and transmon qubits patterned with 193 nm lithography will be used to illustrate how advanced process tools can control critical dimensions of devices, necessary for building larger ensembles of qubits. Advances in the CMOS industry enable superior surface roughness and interface quality to be achieved across the entire 300mm wafer – some examples will be presented. The integration of photonic circuits (waveguides and on-chip cryogenic IR emitters) with superconducting Josephson junctions to enable large-scale neuromorphic computing structures in the near future will be discussed. Ongoing work on developing materials and processes for UV-transparent photonic circuits at 300mm will be presented – such chips could be useful as part of the interface to trapped ion qubits. The talk will wrap up with a discussion of the synergies in technology development, and functionality integration that can be achieved using an advanced fabrication facility.
In the upcoming decades quantum technologies, especially quantum computation, will have a strong influence on industrial, technological, economic, and social progress and are, therefore, considered to be one of the key technologies. The fundamental building blocks for quantum computation are quantum bits (qubits). The superconducting platform offers one of the most promising implementations due to its monolithic character and potential for scalability. Present research around the world primarily focusses on scaling up the number of qubits, so reliable wafer-scale fabrication technologies are mandatory. In this paper, we present our recent developments on wafer-scale fabrication of superconducting quantum circuits including Josephson junctions by the Manhattan-type technology. We discuss fabrication parameters as well as electrical characterization. For arrays out of 50 Josephson junctions with structure dimensions of 200 nm × 200 nm, we achieve a critical current standard deviation of approx. 3% on-chip and 7% on-wafer. We also show first measurement results of so fabricated transmon-type qubits with relaxation and decoherence times ofT1= 12.5 µs andT2= 15.0 µs, respectively. With an increasing number of superconducting qubits and, thus, their input and read-out lines, new challenges arise: Crosstalk between qubits, unwanted modes in the qubit environment, and required interconnections. One way to counteract is the implementation of low inductance connections across coplanar waveguides. This can be realized by aluminum air bridges. In this paper we discuss the air bridges’ fabrication parameters and the impact on the integrated circuits’ elements, e.g., Josephson junctions. We show electrical and superconducting measurements with critical temperatures and critical currents ofTc> 1.0 K andIc> 0.6 mA, respectively.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers 1,2 . As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical 3 . Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing 4 . Moreover, it offers the potential for further upscaling through three-dimensional integration 5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
The performance of superconducting electronic devices such as superconducting quantum bits (qubits) and superconducting quantum interference devices (SQUIDs) strongly relies on high-quality Josephson junctions (JJ) and their integration into surrounding circuit elements. Therefore, a corresponding fabrication technology should allow for the fabrication of all required elements including the JJs, inductances, capacitances and waveguides. For a long time, shadow evaporation technique was the state of the art for the implementation of sub-μ m sized JJs based on aluminum for qubits of high coherence times. Although, the use of a single lithographic step represents a major advantage of this technique. However, shadowing effects limit sample size, device complexity, and thus scalability of the circuitry. To overcome these limitations and to meet the demands of next generation scalable quantum circuits, in this work we introduce our cross -type JJ aluminum technology, where JJs are defined by the overlap of two narrow perpendicular stripes. We discuss the technological challenges, with a focus on our newly developed dry etching process for patterning of the aluminum thin film. Compared to a lift-off based process, this advanced wafer-scale fabrication technology offers a high integration density and the required design flexibility. We will present first results on cross -type aluminum JJs.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers1, 2. As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical3. Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing4. Moreover, it offers the potential for further upscaling through three-dimensional integration5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Josephson tunnel junctions represent a key element in superconducting electronics and quantum circuits. For many years, shadow evaporation by means of Dolan-type bridges has been the state-of-the-art for deep sub- micrometer sized structures. Increasing demand in the number of Josephson junctions, e.g. in qubit circuits and travelling wave parametric amplifiers, requests for a wafer-scale fabrication process with precise control of junction parameters and have led to an advanced lift-off technique called Manhattan-type junction technology in recent years. Herein, we report on the development of a 100 mm wafer-scale fabrication technology for deep sub-micrometer sized Al Josephson junctions with linear dimensions down to 180 nm. The critical currentICof the junctions ranges from about 10 to 120 nA scaling with their linear dimensions. Low temperature transport measurements as well as room-temperature characterization has been used forICand process homogeneity determination of series arrays of up to 50 Josephson junctions. We discuss technology parameters such as yield, on-chip and on-wafer reproducibility of the junction's critical currents as well as main process limitations. Moreover, we present experimental results on the characterization of first transmon-type qubits fabricated using this technology.