Ongoing research at SUNY Polytechnic Institute to enable large scale fabrication of quantum devices with tightly controlled performance characteristics will be presented. Josephson junctions and transmon qubits patterned with 193 nm lithography will be used to illustrate how advanced process tools can control critical dimensions of devices, necessary for building larger ensembles of qubits. Advances in the CMOS industry enable superior surface roughness and interface quality to be achieved across the entire 300mm wafer – some examples will be presented. The integration of photonic circuits (waveguides and on-chip cryogenic IR emitters) with superconducting Josephson junctions to enable large-scale neuromorphic computing structures in the near future will be discussed. Ongoing work on developing materials and processes for UV-transparent photonic circuits at 300mm will be presented – such chips could be useful as part of the interface to trapped ion qubits. The talk will wrap up with a discussion of the synergies in technology development, and functionality integration that can be achieved using an advanced fabrication facility.
Ongoing research at SUNY Polytechnic Institute to enable large scale fabrication of quantum devices with tightly controlled performance characteristics will be presented. Josephson junctions and transmon qubits patterned with 193 nm lithography will be used to illustrate how advanced process tools can control critical dimensions of devices, necessary for building larger ensembles of qubits. Advances in the CMOS industry enable superior surface roughness and interface quality to be achieved across the entire 300mm wafer – some examples will be presented. The integration of photonic circuits (waveguides and on-chip cryogenic IR emitters) with superconducting Josephson junctions to enable large-scale neuromorphic computing structures in the near future will be discussed. Ongoing work on developing materials and processes for UV-transparent photonic circuits at 300mm will be presented – such chips could be useful as part of the interface to trapped ion qubits. The talk will wrap up with a discussion of the synergies in technology development, and functionality integration that can be achieved using an advanced fabrication facility.
Superconducting quantum computing has demonstrated exponential improvements in coherence times over the past two decades, bringing us to the present Noisy Intermediate Scale Quantum (NISQ) era. Improvements in materials and fabrication techniques are still required along with circuit and algorithm innovations to move beyond the NISQ era. We discuss several aspects of the process development work that enables the fabrication of superconducting quantum devices and circuits at 300 mm wafer scale, using materials, processes and tools that are entirely compatible with high-volume integrated circuit fabs. Damascene structures of superconducting tantalum and aluminum (embedded in high resistivity silicon substrates) are described along with examples of process control. The use of such structures for coplanar waveguide resonators in quantum circuits is described, along with modifications to enable integration of normal metal traps to mitigate quasiparticle poisoning. This paper also includes a description of the considerable process development required to enable ALD-TaN based Josephson junctions fabricated with entirely 300 mm compatible processes, in contrast to the lift-off based processes currently in wide use for qubit fabrication. It concludes with a description of how these efforts help with establishing a Quantum Foundry at NY CREATES (a non-profit organization) that can democratize access to advanced qubit fabrication by offering an open superconducting quantum Process Design Kit (PDK).
In the upcoming decades quantum technologies, especially quantum computation, will have a strong influence on industrial, technological, economic, and social progress and are, therefore, considered to be one of the key technologies. The fundamental building blocks for quantum computation are quantum bits (qubits). The superconducting platform offers one of the most promising implementations due to its monolithic character and potential for scalability. Present research around the world primarily focusses on scaling up the number of qubits, so reliable wafer-scale fabrication technologies are mandatory. In this paper, we present our recent developments on wafer-scale fabrication of superconducting quantum circuits including Josephson junctions by the Manhattan-type technology. We discuss fabrication parameters as well as electrical characterization. For arrays out of 50 Josephson junctions with structure dimensions of 200 nm × 200 nm, we achieve a critical current standard deviation of approx. 3% on-chip and 7% on-wafer. We also show first measurement results of so fabricated transmon-type qubits with relaxation and decoherence times ofT1= 12.5 µs andT2= 15.0 µs, respectively. With an increasing number of superconducting qubits and, thus, their input and read-out lines, new challenges arise: Crosstalk between qubits, unwanted modes in the qubit environment, and required interconnections. One way to counteract is the implementation of low inductance connections across coplanar waveguides. This can be realized by aluminum air bridges. In this paper we discuss the air bridges’ fabrication parameters and the impact on the integrated circuits’ elements, e.g., Josephson junctions. We show electrical and superconducting measurements with critical temperatures and critical currents ofTc> 1.0 K andIc> 0.6 mA, respectively.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers 1,2 . As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical 3 . Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing 4 . Moreover, it offers the potential for further upscaling through three-dimensional integration 5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Quantum computing aims to leverage the principles of quantum mechanics to achieve superior information processing capabilities beyond the limits of today's computers. These machines have the potential to efficiently simulate quantum mechanical systems, revolutionizing the development of new materials, drug discovery, and fundamental physics research. Additionally, algorithms such as prime factorization and unstructured data search offer significant speed-ups on quantum computers, enhancing computational capabilities beyond current limits. The first experimental demonstrations of this central idea have sparked significant excitement and expectation in society. Superconducting circuit hardware technologies, which implement quantum computers, are rapidly maturing and transitioning from physics laboratories to industrial fabrication plants. This work aims to bridge the gap between physics laboratory fabrication techniques and industrial standards. Here, the approach starts from complementary metal-oxide-semiconductor (CMOS) compatible processes, optimized using insights from the decades of laboratory development. In particular, two alternative Josephson junction (JJ) fabrication methods are explored, the overlap junction and tri-layer junction approaches, that do not rely on the standard angled evaporation and lift-off processes. These CMOS-compatible fabrication processes are benchmarked for quality and uniformity, using superconducting resonators and qubits to probe material defects and process variability. Device metrics are used to identify and optimize the most critical fabrication steps. Using these methods, a successful overlap JJ qubit fabrication flow is demonstrated with industry standard tools on 300 mm wafer scale, achieving an initial qubit yield of 98.25%. Several devices exhibit lifetimes and coherence times exceeding 100 microseconds, comparable to state-of-the-art devices. Extensive across-wafer measurements and analysis provide insights into limiting factors such as material defects at device interfaces, identifying avenues for continued improvements. The second method, the tri-layer JJ approach, has the potential for defect-free devices with CMOS-grade uniformity by growing epitaxial junctions, patterned with advanced lithography and dry-etch techniques. However, subsequent metallization steps introduce detrimental microwave losses compromising the pristine junctions. Here, a novel tri-layer qubit design is proposed, the tri-layer merged element transmon (tri-MET), which eliminates further processing beyond pristine junction deposition and patterning. The new device is demonstrated in simulation, and initial fabrication steps are presented. In summary, this thesis presents key breakthroughs in superconducting qubit fabrication methods, providing evidence for the viability of industrial methods to fabricate high-coherence superconducting qubits. Further work will focus on addressing interface defects, improving junction uniformity, and incorporating three-dimensional integration techniques to enable large-scale quantum processors for computations beyond the classical limits.
Abstract The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers1, 2. As the complexity of quantum processors continues to grow, the need for stringent fabrication tolerances becomes increasingly critical3. Utilizing advanced industrial fabrication processes could facilitate the necessary level of fabrication control to support the continued scaling of quantum processors. However, at present, these industrial processes are not optimized to produce high-coherence devices, nor are they a priori compatible with the approaches commonly used to make superconducting qubits. Here we demonstrate superconducting transmon qubits manufactured in a 300 mm complementary metal–oxide–semiconductor (CMOS) pilot line using industrial fabrication methods, with resulting relaxation and coherence times exceeding 100 μs. We show across-wafer, large-scale statistics of coherence, yield, variability and ageing that confirm the validity of our approach. The presented industry-scale fabrication process, which uses only optical lithography and reactive-ion etching, has a performance and yield in line with conventional laboratory-style techniques utilizing metal lift-off, angled evaporation and electron-beam writing4. Moreover, it offers the potential for further upscaling through three-dimensional integration5 and more process optimization. This result marks the advent of an alternative and new, large-scale, truly CMOS-compatible fabrication method for superconducting quantum computing processors.
Building quantum computers requires not only a large number of qubits with high fidelity and low variability, but also a large amount of analog and digital components to drive the qubits. Larger arrays of solid-state qubits with high fidelity and low variability require improvements in fabrication processes and array layout design co-optimized with the underlying hardware technology. Here we outline progress on 300mm fabrication of qubit devices and on classical CMOS components to enable the quantum system. We describe work on superconducting qubits and spin qubits in Si, both types of devices fabricated on 300mm experimental platforms and discuss challenges related to variability. Massive electrical characterization is key over wide temperature range is key to enabling system upscaling for QC.