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International SoC Design Conference

0.85 mW, 8-bit, 1GS/s, 58dB SFDR Cryogenic DAC for Superconducting Qubit Control Applications

Chan Kuen Sim, Aarthy Mani, Anh Tuan Do

Published Oct 25, 2023• 0 citations
Publisher

Abstract

This work reports a 8-bit cryogenic digital-to-analog converter (DAC) for qubit control applications. To mitigate the excessive process variations of transistor at cryogenic temperature, we propose a capacitive DAC (CDAC) to utilize the temperature-invariant and better matching properties of MOM-cap devices. Our simulation results showed that SFDR of the CDAC only drops by 1.9dB (from 59.9dBc at 300K to 58dBc at 4K) which is much smaller than 8.5dB change for current steering DAC. This suggests that our proposed CDAC is a promising candidate for cryogenic qubit control applications.

DOI
10.1109/isocc59558.2023.10396606

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This work reports a 8-bit cryogenic digital-to-analog converter (DAC) for qubit control applications. To mitigate the excessive process variations of transistor at cryogenic temperature, we propose a capacitive DAC (CDAC) to utilize the temperature-invariant and better matching properties of MOM-cap devices. Our simulation results showed that SFDR of the CDAC only drops by 1.9dB (from 59.9dBc at 300K to 58dBc at 4K) which is much smaller than 8.5dB change for current steering DAC. This suggests that our proposed CDAC is a promising candidate for cryogenic qubit control applications.
This paper presents the design and test results of a CMOS current-based Digital to Analog Converter (DAC) that operates at cryogenic temperatures and that can be used to precisely control the amount of flux coupled to qubits or that can be used in the readout of superconducting circuits. The current pulse output can be controlled in terms of its amplitude, rise and fall slopes, via digital controls, and pulse width, via external triggers, while driving a superconducting circuit. The design has been implemented in a planar 90 nm CMOS process and test results closely match circuit predictions. The solution's wide degree of digital tunability affords potential application of the same device to many types of quantum circuits, beyond those discussed here. Due to the wide-ranging flexibility of digital CMOS control, we envision that this DAC design will enable the next generation of high-fidelity cryo-CMOS control architectures for superconducting qubits.
This article presents a cryogenic transmon qubit state controller integrated circuit (IC) working at a temperature of 3.5 K for superconducting quantum computing (QC) applications. The qubit state controller IC comprises a polar-modulation-based XY -path driver and a current-steering digital-to-analog converter (DAC)-basedZ{Z}Z-path driver. To generate the XY -path driving pulse with arbitrary envelopes in the frequency range of 4–6 GHz, a switched-capacitor digital power amplifier (DPA) is adopted for amplitude modulation, and an injection locking local oscillator (IL-LO) with a constant-slope digital-to-time-converter (DTC) is used for open-loop phase modulation. With the proposed DPA and IL-LO, the controller can control a qubit with a compact architecture. Fabricated in the 28-nm bulk CMOS process, the controller IC occupies an active die area of 0.9 mm2 per driving channel. The controller achieves a spurious-free dynamic range (SFDR) of 40 dB for a 1 GS/s XY -path driver and an SFDR of 48 dB for a 1 GS/sZ{Z}Z-path driver at 3.5 K. The controller consumes a power of 13.7 mW per qubit. A Rabi experiment at 13.9 MHz, a Ramsey experiment at 3.09 MHz, and a T1 experiment at 15.87μs\mu \text{s}μsare conducted using the presented controller IC at 3.5 K to control the transmon superconducting qubit at 10 mK directly.
This article presents a 4 K cryo-CMOS RF-DAC based super-heterodyne transmitter for superconducting-qubit control. The transmitter integrates an RF-DAC based XY-path driver for quantum state manipulation and a current-steering DAC based Z-path driver for flux-bias control. To balance wideband frequency coverage and power consumption, the XY path separates programmable intermediate-frequency (IF) waveform synthesis from final microwave frequency translation. A 10-bit dual-mode RF-DAC first generates wide-IF control pulses, followed by a mixer for up-conversion to the qubit-frequency. By digitally selecting the non-return-to-zero (NRZ) or mixing (MIX) mode according to the target IF range, the RF-DAC exploits different Nyquist zones to extend the usable IF range without proportionally increasing the sampling clock frequency, enabling flexible and FDM-compatible qubit manipulation without increasing too much power. To mitigate RF-DAC current-cell mismatches under cryogenic operation, a mean-absolute-error (MAE)-based foreground calibration technique is proposed. The fully integrated controller is fabricated in a 28-nm CMOS process. The prototype is measured with ~1 GHz IF bandwidth and 8 GHz RF bandwidth under 46 mW power dissipation at the 4-K stage, and it achieves an SFDR of 33.24–41.62 dB within the 4–8 GHz. The ASIC is installed in a dilution refrigerator as a replacement of the classical control instrument, the experiment results further verify the functionality of the ASIC.
This article presents a cryogenic quantum interface chipset at 3.5 K for superconducting transmon qubit operations. The chipset comprises a phase-detection readout and a phase-shifter-based polar-modulation controller with flexible scalability. With the proposed phase-detection readout scheme, a 9-bit time-to-digital converter (TDC)-based state detector is used to read out the qubit state by detecting the phase difference between the stimulus signal and the reflected signal. A low-IF N-path filter-based receiver and a multi-tone transmitter are co-designed to enable frequency-division multiplexing (FDM) dispersive readout of multiple qubits. A phase-shifter-based polar-modulation XY-driver is developed with support for fast phase quantum gate operation and derivative-removal-by-adiabatic-gate (DRAG) pulse generation. The Z-driver is realized using a static digital-to-analog converter (DAC) array and a 10-bit dynamic DAC for power efficiency. Fabricated in a 28-nm bulk CMOS process, the chipset occupies a die area of 4.6 mm2. The readout RX achieves a noise temperature of 40 K with a gain of 45–83 dB and a bandwidth of 1.2 GHz. The readout RX consumes 32% less power than state-of-the-art designs. The measured total readout power for simultaneous detection of two qubits is 12.2 mW, which is the lowest among readouts with a similar integration level. In addition, the controller achieves a spurious-free dynamic range (SFDR) of 49 dB for a 1-GS/s Z-driver and an SNR of 42 dB for a 1-GS/s XY-driver. The XY-driver consumes 4.3 mW per qubit under active control. Verified with practical transmon qubits, the readout fidelity exceeds 92.6%, approaching that of commercial instruments. A Rabi experiment at 5.61/6.36 MHz, a Ramsey experiment at 4.1 MHz, and a T1 experiment at9.98 μ9.98~{\mu }9.98 μs are also successfully observed using the proposed chipset at 3.5 K.
Scaling superconducting quantum processors is increasingly constrained by the wiring, heat load, and calibration overhead associated with delivering high-resolution analog signals from room temperature to qubits at millikelvin temperature. Here we demonstrate a superconducting digital-to-analog converter (DAC) integrated with high-coherence fluxonium qubits in a multi-chip module architecture. The DACs generate persistent analog flux signals for tuning qubit parameters and are programmed deterministically using single-flux-quantum (SFQ) pulses, providing a digital interface compatible with established SFQ routing and demultiplexing technologies. Operating at millikelvin temperature, the DACs enable in-situ tuning of fluxonium qubits without measurable degradation of qubit coherence. The presented device provides a static control primitive for flux-tunable qubits, enabling parameter homogenization and eliminating the need for individual room-temperature DC bias lines. These results establish SFQ-programmable millikelvin DACs as a building block for digitally controlled superconducting quantum processors.
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra energy efficient data conversion architectures that remain functional at deep cryogenic temperatures.In this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a novel quantum enhanced Josephson junction field effect transistor (JJFET).Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current controlled superconducting devices while aligning naturally with CMOS style design methodologies.Building on our previously developed Verilog A compact model calibrated to experimental data, we design and simulate a three bit JJFET based flash ADC.The core comparator block is realized through careful bias current selection and augmented with a three terminal nanocryotron to precisely define reference voltages.Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic level restoration across stages.Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage driven superconducting mixed signal circuits.This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum classical co-processors, low-power AI accelerators, and next generation energy constrained computing platforms.