Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Chinese Physics B

Hardware for multi-superconducting qubit control and readout*

Zhan Wang, Hai Yang Yu, Rongli Liu, Xiao Ma, Xueyi Guo, Zhongcheng Xiang, Pengtao Song, Luhong Su, Yirong Jin, Dongning Zheng

Published May 24, 2021• 6 citations
Publisher

Abstract

We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices. The hardware system is based on the design ideas of good scalability, high synchronization and low latency. The system, housed inside a VPX-6U chassis, includes multiple arbitrary-waveform generator (AWG) channels, analog-digital-converter (ADC) channels as well as direct current source channels. The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis, and control and readout of more and more qubit can be carried out by interconnecting the chassis. By using field programmable gate array (FPGA) processors, the system incorporates three features that are specifically useful for superconducting qubit research. Firstly, qubit signals can be processed using the on-board FPGA after being acquired by ADCs, significantly reducing data processing time and data amount for storage and transmission. Secondly, different output modes, such as direct output and sequential output modes, of AWG can be implemented with pre-encoded FPGA. Thirdly, with data acquisition ADCs and controlAWGs jointly controlled by the same FPGA, the feedback latency can be reduced, and in ourtest a 178.4 ns latency time is realized. This is very useful for future quantum feedback experiments. Finally, we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.

DOI
10.1088/1674-1056/ac0425

Related papers

FPGA-based electronic system for the control and readout of superconducting quantum processors

Yuchen Yang, Zhongtao Shen, Xing Zhu +6 more

Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5 ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125 ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.

arXiv:2110.07965•Review of Scientific Instruments•Jul 1, 2022•31 citations

An FPGA-Based Low Latency AWG for Superconducting Quantum Computers

Yuchen Yang, Zhongtao Shen, Xing Zhu +3 more

This paper reports the development of a low-latency arbitrary waveform generator (AWG), which is suitable for the control and measurement of superconducting quantum computers. It can generate qubit control signals and measurement signals in real time. Compared with commercial AWG, our AWG has less latency and higher analog bandwidth. Compressing latency can reduce system feedback time, and higher analog bandwidth improves the system's integration by mounting more qubits on the readout line. The AWG integrates four high-speed digital-to-analog converters (DACs), phase-locked loop (PLL) circuits, field-programmable gate arrays (FPGAs), and related circuits into a standard PXI 3U board. The waveform generator module, communication interface module, clock module, and configuration module are realized utilizing the FPGA. The FPGA-based hardware architecture enables AWG to be flexibly configured to meet the various needs of quantum experiments. The four-channel AWG has a 2-GSa/s sampling rate, a 14-bit resolution, and 500 MHz bandwidth. The jitter in the AWG output waveform is approximately 3 ps; the latency of the AWG (the time from the feedback trigger received until a feedback pulse is generated) is approximately 55 ns. These designs form the basis of realizing control system for large-scale quantum computing.

IEEE International Instrumentation and Measurement Technology Conference•May 17, 2021•5 citations

Low-latency readout electronics for dynamic superconducting quantum computing

Cheng Guo, Jin Lin, Lianchen Han +9 more

Dynamic quantum computing can support quantum error correction circuits to build a large general-purpose quantum computer, which requires electronic instruments to perform the closed-loop operation of readout, processing, and control within 1% of the qubit coherence time. In this paper, we present low-latency readout electronics for dynamic superconducting quantum computing. The readout electronics use a low-latency analog-to-digital converter to capture analog signals, a field-programmable gate array (FPGA) to process digital signals, and the general I/O resources of the FPGA to forward the readout results. Running an algorithm based on the design of multichannel parallelism and single instruction multiple data on an FPGA, the readout electronics achieve a readout latency of 40 ns from the last sample input to the readout valid output. The feedback data link for cross-instrument communication shows a communication latency of 48 ns when 16 bits of data are transmitted over a 2 m-length cable using a homologous clock to drive the transceiver. With codeword-based triggering mechanisms, readout electronics can be used in dynamic superconducting quantum computing.

AIP Advances•Apr 1, 2022•9 citations

Superconducting qubit readout and control system based on FPGA and development of a pulse sequencer

BOVE, LEONARDO

This thesis presents the development of a superconducting qubit control and readout system based on FPGA technology, with a focus on the design of a pulse sequencer and the integration of frequency-multiplexed control. The system leverages the Quantum Instrumentation Control Kit (QICK), an open-source Xilinx RFSoC-based platform capable of direct digital synthesis and acquisition of microwave signals up to 10 GHz. The QICK firmware was extended to support the simultaneous generation and readout of multiple frequency-multiplexed tones, enabling the control and measurement of several qubits coupled to a shared feedline. This approach optimizes the number of controllable qubits relative to the available ADC and DAC resources on the RFSoC 4x2 board. Furthermore, this work includes the development of Qubase, a Python-based pulse sequencer that allows users to easily define and execute complex sequences of control and measurement pulses through the QICK Python interface. The resulting architecture is both flexible and scalable, providing a foundation for efficient multi-qubit experiments and enabling advanced techniques such as quantum error correction and real-time feedback.

•Sep 27, 2025•0 citations

Distributed Processor for FPGA-based Superconducting Qubit Control

Neelay Fruitwala, Yilun Xu, Ravi Naik +2 more

Quantum circuits utilizing real time feedback techniques (such as active reset and mid-circuit measurement) are a powerful tool for NISQ-era quantum computing. Such techniques are crucial for implementing error correction protocols, and can reduce the resource requirements of certain quantum algorithms. Realizing these capabilities requires flexible, low-latency classical control. We present the development of an open-source FPGA (field-programmable gate array) based processor for pulse-level qubit control. Our processor is designed primarily as an upgrade to QubiC, an open source qubit control platform, but can also be adapted to other systems. The processor is distributed in nature, with one core per arbitrary waveform generator (AWG); simplifying the design and allowing for straightforward scaling. Each processor core implements an instruction set consisting of timed pulse commands as well as simple arithmetic and branching instructions. Our design also includes interfaces for synchronizing the different cores and requesting/receiving (optionally processed) measurement results. Together, these features will allow a user to program arbitrary control flow within a quantum circuit based on previous measurement results. In this poster, we detail our design along with the expected resource utilization on the Xilinx Virtex 7 FPGA, and present pulse-level simulations of our system in the context of a simple feedback experiment.

IEEE International Conference on Quantum Computing and Engineering (QCE)•Sep 1, 2022•4 citations

A Hardware-Accelerated Qubit Control System for Quantum Information Processing

Nizar Messaoudi, Clayton Crocker, Marc Almendros

In this paper we present a flexible, high-performance, integrated qubit control system using modular PXIe equipment. To manipulate qubits, a classical control system is required to generate and acquire a mix of baseband, radio frequency, and/or optical signals, with the specific mix different for each qubit technology. Typically, a quantum system requires many of these signals with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. The proposed system is scalable to hundreds of channels, all of them being phase coherent and fully time-synchronized.The system includes a programmable real-time sequencer for precise execution timing and decision making; and open FPGA capabilities for custom Digital Signal Processing (DSP) by hardware. Using the latter, we present FPGA IP to generate one-/two-qubit gates efficiently with the AWG, and to analyze high-frequency signals to measure the qubit states in real time on the digitizers. This IP features very low latencies for Quantum Error Correction (QEC) and Frequency Division Multiplexing (FDM) capabilities, among others.

Conference on Design of Circuits and Integrated Systems•Nov 18, 2020•6 citations
We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices. The hardware system is based on the design ideas of good scalability, high synchronization and low latency. The system, housed inside a VPX-6U chassis, includes multiple arbitrary-waveform generator (AWG) channels, analog-digital-converter (ADC) channels as well as direct current source channels. The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis, and control and readout of more and more qubit can be carried out by interconnecting the chassis. By using field programmable gate array (FPGA) processors, the system incorporates three features that are specifically useful for superconducting qubit research. Firstly, qubit signals can be processed using the on-board FPGA after being acquired by ADCs, significantly reducing data processing time and data amount for storage and transmission. Secondly, different output modes, such as direct output and sequential output modes, of AWG can be implemented with pre-encoded FPGA. Thirdly, with data acquisition ADCs and controlAWGs jointly controlled by the same FPGA, the feedback latency can be reduced, and in ourtest a 178.4 ns latency time is realized. This is very useful for future quantum feedback experiments. Finally, we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.
Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5 ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125 ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.
This paper reports the development of a low-latency arbitrary waveform generator (AWG), which is suitable for the control and measurement of superconducting quantum computers. It can generate qubit control signals and measurement signals in real time. Compared with commercial AWG, our AWG has less latency and higher analog bandwidth. Compressing latency can reduce system feedback time, and higher analog bandwidth improves the system's integration by mounting more qubits on the readout line. The AWG integrates four high-speed digital-to-analog converters (DACs), phase-locked loop (PLL) circuits, field-programmable gate arrays (FPGAs), and related circuits into a standard PXI 3U board. The waveform generator module, communication interface module, clock module, and configuration module are realized utilizing the FPGA. The FPGA-based hardware architecture enables AWG to be flexibly configured to meet the various needs of quantum experiments. The four-channel AWG has a 2-GSa/s sampling rate, a 14-bit resolution, and 500 MHz bandwidth. The jitter in the AWG output waveform is approximately 3 ps; the latency of the AWG (the time from the feedback trigger received until a feedback pulse is generated) is approximately 55 ns. These designs form the basis of realizing control system for large-scale quantum computing.
Dynamic quantum computing can support quantum error correction circuits to build a large general-purpose quantum computer, which requires electronic instruments to perform the closed-loop operation of readout, processing, and control within 1% of the qubit coherence time. In this paper, we present low-latency readout electronics for dynamic superconducting quantum computing. The readout electronics use a low-latency analog-to-digital converter to capture analog signals, a field-programmable gate array (FPGA) to process digital signals, and the general I/O resources of the FPGA to forward the readout results. Running an algorithm based on the design of multichannel parallelism and single instruction multiple data on an FPGA, the readout electronics achieve a readout latency of 40 ns from the last sample input to the readout valid output. The feedback data link for cross-instrument communication shows a communication latency of 48 ns when 16 bits of data are transmitted over a 2 m-length cable using a homologous clock to drive the transceiver. With codeword-based triggering mechanisms, readout electronics can be used in dynamic superconducting quantum computing.
This thesis presents the development of a superconducting qubit control and readout system based on FPGA technology, with a focus on the design of a pulse sequencer and the integration of frequency-multiplexed control. The system leverages the Quantum Instrumentation Control Kit (QICK), an open-source Xilinx RFSoC-based platform capable of direct digital synthesis and acquisition of microwave signals up to 10 GHz. The QICK firmware was extended to support the simultaneous generation and readout of multiple frequency-multiplexed tones, enabling the control and measurement of several qubits coupled to a shared feedline. This approach optimizes the number of controllable qubits relative to the available ADC and DAC resources on the RFSoC 4x2 board. Furthermore, this work includes the development of Qubase, a Python-based pulse sequencer that allows users to easily define and execute complex sequences of control and measurement pulses through the QICK Python interface. The resulting architecture is both flexible and scalable, providing a foundation for efficient multi-qubit experiments and enabling advanced techniques such as quantum error correction and real-time feedback.
Quantum circuits utilizing real time feedback techniques (such as active reset and mid-circuit measurement) are a powerful tool for NISQ-era quantum computing. Such techniques are crucial for implementing error correction protocols, and can reduce the resource requirements of certain quantum algorithms. Realizing these capabilities requires flexible, low-latency classical control. We present the development of an open-source FPGA (field-programmable gate array) based processor for pulse-level qubit control. Our processor is designed primarily as an upgrade to QubiC, an open source qubit control platform, but can also be adapted to other systems. The processor is distributed in nature, with one core per arbitrary waveform generator (AWG); simplifying the design and allowing for straightforward scaling. Each processor core implements an instruction set consisting of timed pulse commands as well as simple arithmetic and branching instructions. Our design also includes interfaces for synchronizing the different cores and requesting/receiving (optionally processed) measurement results. Together, these features will allow a user to program arbitrary control flow within a quantum circuit based on previous measurement results. In this poster, we detail our design along with the expected resource utilization on the Xilinx Virtex 7 FPGA, and present pulse-level simulations of our system in the context of a simple feedback experiment.
In this paper we present a flexible, high-performance, integrated qubit control system using modular PXIe equipment. To manipulate qubits, a classical control system is required to generate and acquire a mix of baseband, radio frequency, and/or optical signals, with the specific mix different for each qubit technology. Typically, a quantum system requires many of these signals with a high degree of synchronization and phase coherence, and increasingly needs real-time data processing and on-the-fly sequencing capabilities for feedback experiments. The proposed system is scalable to hundreds of channels, all of them being phase coherent and fully time-synchronized.The system includes a programmable real-time sequencer for precise execution timing and decision making; and open FPGA capabilities for custom Digital Signal Processing (DSP) by hardware. Using the latter, we present FPGA IP to generate one-/two-qubit gates efficiently with the AWG, and to analyze high-frequency signals to measure the qubit states in real time on the digitizers. This IP features very low latencies for Quantum Error Correction (QEC) and Frequency Division Multiplexing (FDM) capabilities, among others.