This thesis presents the development of a superconducting qubit control and readout system based on FPGA technology, with a focus on the design of a pulse sequencer and the integration of frequency-multiplexed control. The system leverages the Quantum Instrumentation Control Kit (QICK), an open-source Xilinx RFSoC-based platform capable of direct digital synthesis and acquisition of microwave signals up to 10 GHz. The QICK firmware was extended to support the simultaneous generation and readout of multiple frequency-multiplexed tones, enabling the control and measurement of several qubits coupled to a shared feedline. This approach optimizes the number of controllable qubits relative to the available ADC and DAC resources on the RFSoC 4x2 board. Furthermore, this work includes the development of Qubase, a Python-based pulse sequencer that allows users to easily define and execute complex sequences of control and measurement pulses through the QICK Python interface. The resulting architecture is both flexible and scalable, providing a foundation for efficient multi-qubit experiments and enabling advanced techniques such as quantum error correction and real-time feedback.
This thesis presents the development of a superconducting qubit control and readout system based on FPGA technology, with a focus on the design of a pulse sequencer and the integration of frequency-multiplexed control. The system leverages the Quantum Instrumentation Control Kit (QICK), an open-source Xilinx RFSoC-based platform capable of direct digital synthesis and acquisition of microwave signals up to 10 GHz. The QICK firmware was extended to support the simultaneous generation and readout of multiple frequency-multiplexed tones, enabling the control and measurement of several qubits coupled to a shared feedline. This approach optimizes the number of controllable qubits relative to the available ADC and DAC resources on the RFSoC 4x2 board. Furthermore, this work includes the development of Qubase, a Python-based pulse sequencer that allows users to easily define and execute complex sequences of control and measurement pulses through the QICK Python interface. The resulting architecture is both flexible and scalable, providing a foundation for efficient multi-qubit experiments and enabling advanced techniques such as quantum error correction and real-time feedback.
We introduce a Xilinx RF System-on-Chip (RFSoC)-based qubit controller (called the Quantum Instrumentation Control Kit, or QICK for short), which supports the direct synthesis of control pulses with carrier frequencies of up to 6 GHz. The QICK can control multiple qubits or other quantum devices. The QICK consists of a digital board hosting an RFSoC field-programmable gate array, custom firmware, and software and an optional companion custom-designed analog front-end board. We characterize the analog performance of the system as well as its digital latency, important for quantum error correction and feedback protocols. We benchmark the controller by performing standard characterizations of a transmon qubit. We achieve an average gate fidelity of Favg=99.93%. All of the schematics, firmware, and software are open-source.
We present FIREQ (FPGA Instrumentation for Readout and Qubit control), an open-source RFSoC-based framework for the control and readout of superconducting qubits. FIREQ combines a modular AXI-compliant firmware architecture with a PYNQ-based software stack designed to support extensible hardware integration, deterministic experiment timing, and low-overhead execution of repeated calibration and characterization workflows. The firmware implements direct RF synthesis and acquisition, trigger-based sequencing, programmable pulse generation, frequency-multiplexed readout, and memory-efficient acquisition and waveform buffering. The software adopts a client-server architecture with streamed data transfer and dependency-aware configuration updates to reduce host-device and reconfiguration overhead during parameter sweeps. On an AMD Zynq UltraScale+ RFSoC ZCU216, FIREQ generates RF pulses up to 9.3 GHz with a pulse-duration resolution of 107 ps and an event-timing resolution of 1.7 ns. FPGA resource utilization is compared with representative open-source RFSoC control frameworks, showing a low BRAM footprint while retaining full-rate I/Q generation and acquisition. The RF output is characterized in terms of phase noise, noise spectral density, and inter-channel timing skew. End-to-end operation is validated on a superconducting qubit through resonator spectroscopy, Rabi, Ramsey, and relaxation measurements, yielding T1 = 6.94 us and T2* = 13.50 us. FIREQ can therefore be used both as a qubit-control platform and as an experimental environment for evaluating alternative control and readout IP architectures.
A scalable control architecture for superconducting quantum processors is essential as the number of qubits increases and coherent multi-qubit operations span beyond the capacity of a single control module. The Quantum Instrumentation Control Kit (QICK), built on AMD RFSoC platforms, offers a flexible open-source framework for pulse-level qubit control but lacks native support for multi-board synchronization, limiting its applicability to mid- and large-scale quantum devices. To overcome this limitation, we introduce Manarat, a scalable multi-board control platform based on QICK that incorporates hardware, firmware, and software enhancements to enable sub-100 ps timing alignment across multiple AMD ZCU216 RFSoC boards. Our system integrates a low-jitter clock distribution network, modifications to the tProcessor, and a synchronization scheme to ensure deterministic alignment of program execution across boards. It also includes a custom analog front-end for flux control that combines high-speed RF signals with software-programmable DC biasing voltages generated by a low-noise, high-precision DAC. These capabilities are complemented by a software stack capable of orchestrating synchronized multi-board experiments and fully integrated with the open-source Qibo framework for quantum device calibration and algorithm execution. We validate Manarat on a 10-qubit superconducting processor controlled by two RFSoC boards, demonstrating reliable execution of synchronized control sequences for cross-board CZ gate calibration. These results confirm that sub-nanosecond synchronization and coherent control are achievable across multiple RFSoC boards, enabling scalable operation of superconducting quantum computers.
We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices. The hardware system is based on the design ideas of good scalability, high synchronization and low latency. The system, housed inside a VPX-6U chassis, includes multiple arbitrary-waveform generator (AWG) channels, analog-digital-converter (ADC) channels as well as direct current source channels. The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis, and control and readout of more and more qubit can be carried out by interconnecting the chassis. By using field programmable gate array (FPGA) processors, the system incorporates three features that are specifically useful for superconducting qubit research. Firstly, qubit signals can be processed using the on-board FPGA after being acquired by ADCs, significantly reducing data processing time and data amount for storage and transmission. Secondly, different output modes, such as direct output and sequential output modes, of AWG can be implemented with pre-encoded FPGA. Thirdly, with data acquisition ADCs and controlAWGs jointly controlled by the same FPGA, the feedback latency can be reduced, and in ourtest a 178.4 ns latency time is realized. This is very useful for future quantum feedback experiments. Finally, we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.
Quantum circuits utilizing real time feedback techniques (such as active reset and mid-circuit measurement) are a powerful tool for NISQ-era quantum computing. Such techniques are crucial for implementing error correction protocols, and can reduce the resource requirements of certain quantum algorithms. Realizing these capabilities requires flexible, low-latency classical control. We have developed a custom FPGA-based processor architecture for QubiC, an open source platform for superconducting qubit control. Our architecture is distributed in nature, and consists of a bank of lightweight cores, each configured to control a small (1-3) number of signal generator channels. Each core is capable of executing parameterized control and readout pulses, as well as performing arbitrary control flow based on mid-circuit measurement results. We have also developed a modular compiler stack and domain-specific intermediate representation for programming the processor. Our representation allows users to specify circuits using both gate and pulse-level abstractions, and includes high-level control flow constructs (e.g. if-else blocks and loops). The compiler stack is designed to integrate with quantum software tools and programming languages, such as TrueQ, pyGSTi, and OpenQASM3. In this work, we will detail the design of both the processor and compiler stack, and demonstrate its capabilities with a quantum state teleportation experiment using transmon qubits at the LBNL Advanced Quantum Testbed.
Quantum circuits utilizing real time feedback techniques (such as active reset and mid-circuit measurement) are a powerful tool for NISQ-era quantum computing. Such techniques are crucial for implementing error correction protocols, and can reduce the resource requirements of certain quantum algorithms. Realizing these capabilities requires flexible, low-latency classical control. We present the development of an open-source FPGA (field-programmable gate array) based processor for pulse-level qubit control. Our processor is designed primarily as an upgrade to QubiC, an open source qubit control platform, but can also be adapted to other systems. The processor is distributed in nature, with one core per arbitrary waveform generator (AWG); simplifying the design and allowing for straightforward scaling. Each processor core implements an instruction set consisting of timed pulse commands as well as simple arithmetic and branching instructions. Our design also includes interfaces for synchronizing the different cores and requesting/receiving (optionally processed) measurement results. Together, these features will allow a user to program arbitrary control flow within a quantum circuit based on previous measurement results. In this poster, we detail our design along with the expected resource utilization on the Xilinx Virtex 7 FPGA, and present pulse-level simulations of our system in the context of a simple feedback experiment.