Dynamic quantum computing can support quantum error correction circuits to build a large general-purpose quantum computer, which requires electronic instruments to perform the closed-loop operation of readout, processing, and control within 1% of the qubit coherence time. In this paper, we present low-latency readout electronics for dynamic superconducting quantum computing. The readout electronics use a low-latency analog-to-digital converter to capture analog signals, a field-programmable gate array (FPGA) to process digital signals, and the general I/O resources of the FPGA to forward the readout results. Running an algorithm based on the design of multichannel parallelism and single instruction multiple data on an FPGA, the readout electronics achieve a readout latency of 40 ns from the last sample input to the readout valid output. The feedback data link for cross-instrument communication shows a communication latency of 48 ns when 16 bits of data are transmitted over a 2 m-length cable using a homologous clock to drive the transceiver. With codeword-based triggering mechanisms, readout electronics can be used in dynamic superconducting quantum computing.
Dynamic quantum computing can support quantum error correction circuits to build a large general-purpose quantum computer, which requires electronic instruments to perform the closed-loop operation of readout, processing, and control within 1% of the qubit coherence time. In this paper, we present low-latency readout electronics for dynamic superconducting quantum computing. The readout electronics use a low-latency analog-to-digital converter to capture analog signals, a field-programmable gate array (FPGA) to process digital signals, and the general I/O resources of the FPGA to forward the readout results. Running an algorithm based on the design of multichannel parallelism and single instruction multiple data on an FPGA, the readout electronics achieve a readout latency of 40 ns from the last sample input to the readout valid output. The feedback data link for cross-instrument communication shows a communication latency of 48 ns when 16 bits of data are transmitted over a 2 m-length cable using a homologous clock to drive the transceiver. With codeword-based triggering mechanisms, readout electronics can be used in dynamic superconducting quantum computing.
Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5 ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125 ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.
We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices. The hardware system is based on the design ideas of good scalability, high synchronization and low latency. The system, housed inside a VPX-6U chassis, includes multiple arbitrary-waveform generator (AWG) channels, analog-digital-converter (ADC) channels as well as direct current source channels. The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis, and control and readout of more and more qubit can be carried out by interconnecting the chassis. By using field programmable gate array (FPGA) processors, the system incorporates three features that are specifically useful for superconducting qubit research. Firstly, qubit signals can be processed using the on-board FPGA after being acquired by ADCs, significantly reducing data processing time and data amount for storage and transmission. Secondly, different output modes, such as direct output and sequential output modes, of AWG can be implemented with pre-encoded FPGA. Thirdly, with data acquisition ADCs and controlAWGs jointly controlled by the same FPGA, the feedback latency can be reduced, and in ourtest a 178.4 ns latency time is realized. This is very useful for future quantum feedback experiments. Finally, we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.
This paper reports the development of a low-latency arbitrary waveform generator (AWG), which is suitable for the control and measurement of superconducting quantum computers. It can generate qubit control signals and measurement signals in real time. Compared with commercial AWG, our AWG has less latency and higher analog bandwidth. Compressing latency can reduce system feedback time, and higher analog bandwidth improves the system's integration by mounting more qubits on the readout line. The AWG integrates four high-speed digital-to-analog converters (DACs), phase-locked loop (PLL) circuits, field-programmable gate arrays (FPGAs), and related circuits into a standard PXI 3U board. The waveform generator module, communication interface module, clock module, and configuration module are realized utilizing the FPGA. The FPGA-based hardware architecture enables AWG to be flexibly configured to meet the various needs of quantum experiments. The four-channel AWG has a 2-GSa/s sampling rate, a 14-bit resolution, and 500 MHz bandwidth. The jitter in the AWG output waveform is approximately 3 ps; the latency of the AWG (the time from the feedback trigger received until a feedback pulse is generated) is approximately 55 ns. These designs form the basis of realizing control system for large-scale quantum computing.
Real-time control and readout are pivotal in superconducting quantum computing, given the imperative for numerous algorithms to perform quantum operations as much as possible within the qubit coherent time. Here, we specifically address the qubit readout, recognized as the most time-consuming operation within our experimental platform, and propose a dynamic adaptive readout method (DARM) to improve the performance of qubit readout. In contrast to a standard readout method (SRM) employing Gaussian Naïve Bayes as a discriminator, the DARM can demonstrate a 22.76% relative improvement on readout fidelity when the readout duration time of both methods is set to be consistent. Furthermore, the DARM can also terminate measurement pulse ahead with a 9.93% relative reduction of measurement pulse length on statistical average. The DARM is implemented on a field-programmable-gate-array-based system, and the electronic processing latency, from the digital processing unit getting the qubit signal to the valid output information, is 52 ns, which is only 4 ns longer than the SRM. Compared with the feedforward neural network readout method, the DARM can work in a pipeline mode with shorter electronic processing latency and lower electronic utilization.
Feedback is a main component of many algorithms for quantum computing and communication. A key requirement for any quantum feedback scheme is that the $l\phantom{\rule{0}{0ex}}a\phantom{\rule{0}{0ex}}t\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}c\phantom{\rule{0}{0ex}}y$ of the feedback loop (i.e. the time between beginning to measure a state and the end of feedback action on the state) must be significantly shorter than the coherence time of the system. In this work a superconducting qubit is initialized in its ground state by active feedback, using a field-programmable gate array (FPGA) with very short latency. This in-depth discussion of the FPGA-based processing unit provides a useful reference for future development of feedback electronics for quantum systems.
We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.