Low-Latency Digital Signal Processing for Feedback and Feedforward in Quantum Computing and Communication
Yves Salathé, Philipp Kurpiers, Thomas M. Karg, Claus Lang, Christian Kraglund Andersen, Abdulkadir Akın, Sebastian Krinner, Christopher Eichler, Andreas J. Wallraff
Feedback is a main component of many algorithms for quantum computing and communication. A key requirement for any quantum feedback scheme is that the $l\phantom{\rule{0}{0ex}}a\phantom{\rule{0}{0ex}}t\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}c\phantom{\rule{0}{0ex}}y$ of the feedback loop ($i.e.$ the time between beginning to measure a state and the end of feedback action on the state) must be significantly shorter than the coherence time of the system. In this work a superconducting qubit is initialized in its ground state by active feedback, using a field-programmable gate array (FPGA) with very short latency. This in-depth discussion of the FPGA-based processing unit provides a useful reference for future development of feedback electronics for quantum systems.
Feedback is a main component of many algorithms for quantum computing and communication. A key requirement for any quantum feedback scheme is that the l\phantom{\rule{0}{0ex}}a\phantom{\rule{0}{0ex}}t\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}c\phantom{\rule{0}{0ex}}y of the feedback loop (i.e. the time between beginning to measure a state and the end of feedback action on the state) must be significantly shorter than the coherence time of the system. In this work a superconducting qubit is initialized in its ground state by active feedback, using a field-programmable gate array (FPGA) with very short latency. This in-depth discussion of the FPGA-based processing unit provides a useful reference for future development of feedback electronics for quantum systems.
Dynamic quantum computing can support quantum error correction circuits to build a large general-purpose quantum computer, which requires electronic instruments to perform the closed-loop operation of readout, processing, and control within 1% of the qubit coherence time. In this paper, we present low-latency readout electronics for dynamic superconducting quantum computing. The readout electronics use a low-latency analog-to-digital converter to capture analog signals, a field-programmable gate array (FPGA) to process digital signals, and the general I/O resources of the FPGA to forward the readout results. Running an algorithm based on the design of multichannel parallelism and single instruction multiple data on an FPGA, the readout electronics achieve a readout latency of 40 ns from the last sample input to the readout valid output. The feedback data link for cross-instrument communication shows a communication latency of 48 ns when 16 bits of data are transmitted over a 2 m-length cable using a homologous clock to drive the transceiver. With codeword-based triggering mechanisms, readout electronics can be used in dynamic superconducting quantum computing.
Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5 ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125 ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.
back offers not just the convenience of streamlined data acquisition, but is an essential element in any quantum computational architecture that requires branching based on measurement outcomes. State-preparation, mitigating the effects of qubit decoherence, and recording the trajectories of quantum systems are just a few of the many potential applications of real-time feedback. Photon number parity measurements of cat states in superconducting resonators are a particularly useful platform for demonstrating the clear advantages of having sophisticated feedback schemes to enhance the performance a proposed error-correction protocol [Leghtas et.al. PRL 2013]. In a cQED architecture, where a transmon qubit is coupled to two superconducting cavities, we present a field-programmable gate array (FPGA) device capable of making decisions and calculations with latency times far shorter than the lifetimes of any of the system’s constituents. This level of performance opens the door to realizing many complex, previously unfeasible, experiments in superconducting qubit systems.
This chapter covers the development of feedback control of superconducting qubits using projective measurement and a discrete set of conditional actions, here referred to as digital feedback. We begin with an overview of the applications of digital feedback in quantum computing. We then introduce an implementation of high-fidelity projective measurement of superconducting qubits. This development lays the ground for closed-loop control based on the binary measurement result. A first application of digital feedback control is fast and deterministic qubit reset, allowing the repeated initialization of a qubit more than an order of magnitude faster than its relaxation rate. A second application employs feedback in a multi-qubit setting to convert the generation of entanglement by parity measurement from probabilistic to deterministic, targeting an entangled state with the desired parity every time.
This paper reports the development of a low-latency arbitrary waveform generator (AWG), which is suitable for the control and measurement of superconducting quantum computers. It can generate qubit control signals and measurement signals in real time. Compared with commercial AWG, our AWG has less latency and higher analog bandwidth. Compressing latency can reduce system feedback time, and higher analog bandwidth improves the system's integration by mounting more qubits on the readout line. The AWG integrates four high-speed digital-to-analog converters (DACs), phase-locked loop (PLL) circuits, field-programmable gate arrays (FPGAs), and related circuits into a standard PXI 3U board. The waveform generator module, communication interface module, clock module, and configuration module are realized utilizing the FPGA. The FPGA-based hardware architecture enables AWG to be flexibly configured to meet the various needs of quantum experiments. The four-channel AWG has a 2-GSa/s sampling rate, a 14-bit resolution, and 500 MHz bandwidth. The jitter in the AWG output waveform is approximately 3 ps; the latency of the AWG (the time from the feedback trigger received until a feedback pulse is generated) is approximately 55 ns. These designs form the basis of realizing control system for large-scale quantum computing.
Active reset of qubits is a critical step toward realizing large-scale quantum error correction(QEC) algorithms, as it enables rapid initialization of qubits to the ground state and enhances the accuracy of quantum computing. In this paper, we address the issues of existing active reset schemes that require faster feedback speeds, higher flexibility, and integration in multichannel operations. We propose a highly scalable, integrated, low-latency feedback closed-loop measurement and control system that supports local decision-making and independent judgment. The system achieves precise timing control, parameterized waveform generation, high-fidelity demodulation and decision-making computations, and rapid closed-loop feedback links. Experimental results show that the total latency of the closed-loop feedback is 243 ns, and the active reset test success rate reaches 99.5%, representing significant improvements in both efficiency and precision compared to traditional passive reset methods. Through modular design, the system supports multi-board expansion and can be adapted for concurrent reset control of large-scale qubit chips.