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IEEE Advanced Information Technology, Electronic and Automation Control Conference (IAEAC)

Research on FPGA-Based Electronic System for Active Reset of Superconducting Qubits

Yaping Lü, Yifei Chen, Maojie Ma, Liyu Tian

Published Aug 8, 2025• 0 citations
Publisher

Abstract

Active reset of qubits is a critical step toward realizing large-scale quantum error correction(QEC) algorithms, as it enables rapid initialization of qubits to the ground state and enhances the accuracy of quantum computing. In this paper, we address the issues of existing active reset schemes that require faster feedback speeds, higher flexibility, and integration in multichannel operations. We propose a highly scalable, integrated, low-latency feedback closed-loop measurement and control system that supports local decision-making and independent judgment. The system achieves precise timing control, parameterized waveform generation, high-fidelity demodulation and decision-making computations, and rapid closed-loop feedback links. Experimental results show that the total latency of the closed-loop feedback is 243 ns, and the active reset test success rate reaches 99.5%, representing significant improvements in both efficiency and precision compared to traditional passive reset methods. Through modular design, the system supports multi-board expansion and can be adapted for concurrent reset control of large-scale qubit chips.

DOI
10.1109/iaeac65194.2025.11166144

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Active reset of qubits is a critical step toward realizing large-scale quantum error correction(QEC) algorithms, as it enables rapid initialization of qubits to the ground state and enhances the accuracy of quantum computing. In this paper, we address the issues of existing active reset schemes that require faster feedback speeds, higher flexibility, and integration in multichannel operations. We propose a highly scalable, integrated, low-latency feedback closed-loop measurement and control system that supports local decision-making and independent judgment. The system achieves precise timing control, parameterized waveform generation, high-fidelity demodulation and decision-making computations, and rapid closed-loop feedback links. Experimental results show that the total latency of the closed-loop feedback is 243 ns, and the active reset test success rate reaches 99.5%, representing significant improvements in both efficiency and precision compared to traditional passive reset methods. Through modular design, the system supports multi-board expansion and can be adapted for concurrent reset control of large-scale qubit chips.
We developed a versatile integrated control and readout instrument for experiments with superconducting quantum bits (qubits), based on a field-programmable gate array (FPGA) platform. Using this platform, we perform measurement-based, closed-loop feedback operations with 428 ns platform latency. The feedback capability is instrumental in realizing active reset initialization of the qubit into the ground state in a time much shorter than its energy relaxation time T1. We show experimental results demonstrating reset of a fluxonium qubit with 99.4 % fidelity, using a readout-and-drive pulse sequence approximately 1. 5 µs long. Compared to passive ground state initialization through thermalization, with the time constant given by T1 = 80 µs, the use of the FPGA-based platform allows us to improve both the fidelity and the time of the qubit initialization by an order of magnitude.
Active reset of qubits is a crucial step in achieving quantum algorithms, particularly in fault-tolerant quantum computing, as it allows qubits to be quickly initialized to the ground state. In this paper, we demonstrate active reset of superconducting qubits using the feedback electronics based on RF switches. We are able to reset the qubit to the ground state in 11.412 µs with a success rate of 99.82%, which is better than the natural relaxation method in terms of both time consumption (180 µs) and success rate (99.61%). The demonstrated method facilitates fast and high-fidelity qubit initialization, holding practical significance for large-scale quantum computation.
Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5 ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125 ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.
Fast, high-fidelity qubit initialization is a key primitive for scalable quantum information processing, but conventional reset protocols either require long relaxation times or discard information contained in continuous measurement records. We demonstrate an adaptive measurement-based reset protocol for superconducting qubits that uses Bayesian inference to update the qubit-state estimate after each readout and dynamically adjust the feedback threshold. Unlike fixed-threshold or repeat-until-success (RUS) protocols, the method utilizes the full analog measurement history, enabling the reset decision to become progressively more conservative as confidence in ground-state preparation increases. Implemented with real-time FPGA-based feedback on a dispersively readout transmon qubit, the protocol achieves a ground-state initialization fidelity of 99.44±0.04%99.44\pm0.04\%99.44±0.04% after a small number of reset rounds. We further compare adaptive reset with RUS strategies in multi-qubit experiments and show that adaptive thresholding provides deterministic reset duration while maintaining a five-qubit simultaneous-reset fidelity of 98.78±0.19%98.78 \pm 0.19\%98.78±0.19%. These results establish Bayesian adaptive thresholding as a practical and scalable route to fast qubit reset in superconducting quantum processors.
This paper reports the development of a low-latency arbitrary waveform generator (AWG), which is suitable for the control and measurement of superconducting quantum computers. It can generate qubit control signals and measurement signals in real time. Compared with commercial AWG, our AWG has less latency and higher analog bandwidth. Compressing latency can reduce system feedback time, and higher analog bandwidth improves the system's integration by mounting more qubits on the readout line. The AWG integrates four high-speed digital-to-analog converters (DACs), phase-locked loop (PLL) circuits, field-programmable gate arrays (FPGAs), and related circuits into a standard PXI 3U board. The waveform generator module, communication interface module, clock module, and configuration module are realized utilizing the FPGA. The FPGA-based hardware architecture enables AWG to be flexibly configured to meet the various needs of quantum experiments. The four-channel AWG has a 2-GSa/s sampling rate, a 14-bit resolution, and 500 MHz bandwidth. The jitter in the AWG output waveform is approximately 3 ps; the latency of the AWG (the time from the feedback trigger received until a feedback pulse is generated) is approximately 55 ns. These designs form the basis of realizing control system for large-scale quantum computing.