Real-time control and readout are pivotal in superconducting quantum computing, given the imperative for numerous algorithms to perform quantum operations as much as possible within the qubit coherent time. Here, we specifically address the qubit readout, recognized as the most time-consuming operation within our experimental platform, and propose a dynamic adaptive readout method (DARM) to improve the performance of qubit readout. In contrast to a standard readout method (SRM) employing Gaussian Naïve Bayes as a discriminator, the DARM can demonstrate a 22.76% relative improvement on readout fidelity when the readout duration time of both methods is set to be consistent. Furthermore, the DARM can also terminate measurement pulse ahead with a 9.93% relative reduction of measurement pulse length on statistical average. The DARM is implemented on a field-programmable-gate-array-based system, and the electronic processing latency, from the digital processing unit getting the qubit signal to the valid output information, is 52 ns, which is only 4 ns longer than the SRM. Compared with the feedforward neural network readout method, the DARM can work in a pipeline mode with shorter electronic processing latency and lower electronic utilization.
Real-time control and readout are pivotal in superconducting quantum computing, given the imperative for numerous algorithms to perform quantum operations as much as possible within the qubit coherent time. Here, we specifically address the qubit readout, recognized as the most time-consuming operation within our experimental platform, and propose a dynamic adaptive readout method (DARM) to improve the performance of qubit readout. In contrast to a standard readout method (SRM) employing Gaussian Naïve Bayes as a discriminator, the DARM can demonstrate a 22.76% relative improvement on readout fidelity when the readout duration time of both methods is set to be consistent. Furthermore, the DARM can also terminate measurement pulse ahead with a 9.93% relative reduction of measurement pulse length on statistical average. The DARM is implemented on a field-programmable-gate-array-based system, and the electronic processing latency, from the digital processing unit getting the qubit signal to the valid output information, is 52 ns, which is only 4 ns longer than the SRM. Compared with the feedforward neural network readout method, the DARM can work in a pipeline mode with shorter electronic processing latency and lower electronic utilization.
Dynamic quantum computing can support quantum error correction circuits to build a large general-purpose quantum computer, which requires electronic instruments to perform the closed-loop operation of readout, processing, and control within 1% of the qubit coherence time. In this paper, we present low-latency readout electronics for dynamic superconducting quantum computing. The readout electronics use a low-latency analog-to-digital converter to capture analog signals, a field-programmable gate array (FPGA) to process digital signals, and the general I/O resources of the FPGA to forward the readout results. Running an algorithm based on the design of multichannel parallelism and single instruction multiple data on an FPGA, the readout electronics achieve a readout latency of 40 ns from the last sample input to the readout valid output. The feedback data link for cross-instrument communication shows a communication latency of 48 ns when 16 bits of data are transmitted over a 2 m-length cable using a homologous clock to drive the transceiver. With codeword-based triggering mechanisms, readout electronics can be used in dynamic superconducting quantum computing.
Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit technology, synchronization in a large-scale system, low-latency execution, and low noise are required for electronic systems. Here, we present a field-programmable gate array (FPGA)-based electronic system with a distributed synchronous clock and trigger architecture. The system supports synchronous control of qubits with jitters of ∼5 ps. We implement a real-time digital signal processing system in the FPGA, enabling precise timing control, arbitrary waveform generation, in-phase and quadrature demodulation for qubit state discrimination, and the generation of real-time qubit-state-dependent trigger signals for feedback/feedforward control. The hardware and firmware low-latency design reduces the feedback/feedforward latency of the electronic system to 125 ns, significantly less than the decoherence times of the qubit. Finally, we demonstrate the functionalities and low-noise performance of this system using a fluxonium quantum processor.
We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices. The hardware system is based on the design ideas of good scalability, high synchronization and low latency. The system, housed inside a VPX-6U chassis, includes multiple arbitrary-waveform generator (AWG) channels, analog-digital-converter (ADC) channels as well as direct current source channels. The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis, and control and readout of more and more qubit can be carried out by interconnecting the chassis. By using field programmable gate array (FPGA) processors, the system incorporates three features that are specifically useful for superconducting qubit research. Firstly, qubit signals can be processed using the on-board FPGA after being acquired by ADCs, significantly reducing data processing time and data amount for storage and transmission. Secondly, different output modes, such as direct output and sequential output modes, of AWG can be implemented with pre-encoded FPGA. Thirdly, with data acquisition ADCs and controlAWGs jointly controlled by the same FPGA, the feedback latency can be reduced, and in ourtest a 178.4 ns latency time is realized. This is very useful for future quantum feedback experiments. Finally, we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.
Quantum processors require rapid and high-fidelity simultaneous measurements of many qubits. While superconducting qubits are among the leading modalities toward a useful quantum processor, their readout remains a bottleneck. Traditional approaches to processing measurement data often struggle to account for crosstalk present in frequency-multiplexed readout, the preferred method to reduce the resource overhead. Recent approaches to address this challenge use neural networks to improve the state-discrimination fidelity. However, they are computationally expensive to train and evaluate, resulting in increased latency and poor scalability as the number of qubits increases. We present an alternative machine learning approach based on next-generation reservoir computing that constructs polynomial features from the measurement signals and maps them to the corresponding qubit states. This method is highly parallelizable, avoids the costly nonlinear activation functions common in neural networks, and supports real-time training, enabling fast evaluation, adaptability, and scalability. Despite its lower computational complexity, our reservoir approach is able to maintain high qubit-state-discrimination fidelity. Relative to traditional methods, our approach achieves error reductions of up to 50% and 11% on single- and five-qubit datasets, respectively, and delivers up to 2.5x crosstalk reduction on the five-qubit dataset. Compared with recent machine-learning methods, evaluating our model requires 100x fewer multiplications for single-qubit and 2.5x fewer for five-qubit models. This work demonstrates that reservoir computing can enhance qubit-state discrimination while maintaining scalability for future quantum processors.
We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.
Fast and accurate qubit-state assignment is essential for feedback, calibration, and error correction in quantum processors. In superconducting platforms, frequency-multiplexed readout makes this task intrinsically multivariate as measured traces can encode crosstalk, qubit-state relaxation events, and other transient nonidealities that are not fully captured by conventional matched filtering. Here, we introduce spiking neural network (SNN) discriminators for superconducting qubit readout. By processing the measurement window in successive time chunks, the networks exploit temporal structure and update classification scores as data arrive, rather than waiting until the end of the readout window. The spiking networks outperform matched-filter discrimination and approach the accuracy of a full-trace artificial neural network. Beyond reaching the performance of artificial neural networks, the key advantage of SNNs is that they provide a streaming, time-resolved estimate of the qubit state that evolves as the readout signal is acquired. Using quantisation-aware training and hls4ml synthesis, we further demonstrate that each FPGA inference update can be completed before the next readout chunk arrives. These results establish spiking neural networks as a promising route to low-latency, real-time qubit readout on FPGA hardware, with broader implications for time-critical quantum-control and scientific-inference applications.