Abstract We present the development of Nb/Al–AlO x /Nb trilayer stacks and the implementation of a full 300 mm process flow for the fabrication of trilayer-based superconducting qubits. Room temperature electrical characterization of tens of thousands of Josephson junctions showed good agreement between blanket resistance-area (RA) product and RA product of processed wafers. Cross-bridge Kelvin resistor structures with dimensions ranging from 200 nm to 1.2 μ m were tested and exhibited excellent yield and exceptionally low resistance variability down to <1%. This result is expected to translate to reduced qubit device variability and improved predictability of qubit transition frequencies at cryogenic temperatures.
Abstract We present the development of Nb/Al–AlO x /Nb trilayer stacks and the implementation of a full 300 mm process flow for the fabrication of trilayer-based superconducting qubits. Room temperature electrical characterization of tens of thousands of Josephson junctions showed good agreement between blanket resistance-area (RA) product and RA product of processed wafers. Cross-bridge Kelvin resistor structures with dimensions ranging from 200 nm to 1.2 μ m were tested and exhibited excellent yield and exceptionally low resistance variability down to <1%. This result is expected to translate to reduced qubit device variability and improved predictability of qubit transition frequencies at cryogenic temperatures.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2 to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
We present the results of an industry-grade fabrication of superconducting qubits on 200 mm wafers utilizing CMOS-established processing methods. By automated waferprober resistance measurements at room temperature, we demonstrate a Josephson junction fabrication yield of 99.7% (shorts and opens) across more than 10000 junctions and a qubit frequency prediction accuracy of 1.6%. In cryogenic characterization, we provide statistical results regarding energy relaxation times of the qubits with a median T1 of up to 100 us and individual devices consistently approaching 200 us in long-term measurements. This represents the best performance reported so far for superconducting qubits fabricated by industry-grade, wafer-level subtractive processes.
Abstract Josephson tunnel junctions form the basis for various superconductor electronic devices. For this reason, enormous efforts are routinely taken to establish and later on maintain a scalable and reproducible wafer-scale manufacturing process for high-quality Josephson junctions. Here, we present an anodization-free fabrication process for Nb/Al-AlO x /Nb cross-type Josephson junctions that requires only a small number of process steps and that is in general intrinsically compatible with wafer-scale fabrication. We show that the fabricated junctions are of very high quality and, compared to other junction types, exhibit not only a significantly reduced capacitance but also an almost rectangular critical current density profile. Our process hence enables the usage of low capacitance Josephson junctions for superconductor electronic devices such as ultra-low noise dc-superconducting quantum interference devices (SQUIDs), microwave SQUID multiplexers based on non-hysteretic rf-SQUIDs and RFSQ circuits.
Josephson tunnel junctions represent a key element in superconducting electronics and quantum circuits. For many years, shadow evaporation by means of Dolan-type bridges has been the state-of-the-art for deep sub- micrometer sized structures. Increasing demand in the number of Josephson junctions, e.g. in qubit circuits and travelling wave parametric amplifiers, requests for a wafer-scale fabrication process with precise control of junction parameters and have led to an advanced lift-off technique called Manhattan-type junction technology in recent years. Herein, we report on the development of a 100 mm wafer-scale fabrication technology for deep sub-micrometer sized Al Josephson junctions with linear dimensions down to 180 nm. The critical currentICof the junctions ranges from about 10 to 120 nA scaling with their linear dimensions. Low temperature transport measurements as well as room-temperature characterization has been used forICand process homogeneity determination of series arrays of up to 50 Josephson junctions. We discuss technology parameters such as yield, on-chip and on-wafer reproducibility of the junction's critical currents as well as main process limitations. Moreover, we present experimental results on the characterization of first transmon-type qubits fabricated using this technology.
We have demonstrated a new planarized all-refractory technology for low Tc superconductivity (PARTS). With the exception of the Nb-AlOx-Nb trilayer preparation, the processing is done almost exclusively within an advanced Si technology fabrication facility. This approach has allowed us to leverage highly off of existing state-of-the-art lithography, metal etching, materials deposition, and planarization capabilities. Using chemical-mechanical polish as the planarization technique we have fabricated Josephson junctions ranging in size from 0.5–100 μm2. Junction quality is excellent with the figure of merit Vm typically exceeding 70 mV. PARTS has yielded fully functional integrated Josephson devices including magnetometers, gradiometers, and soliton oscillators.
Abstract Tantalum and aluminum on sapphire are widely used platforms for qubits of long coherent time. As quantum chips scale up, the number of Josephson junctions on Sapphire increases. Thus, both the uniformity and stability of the junctions are crucial to quantum devices, such as scalable superconducting quantum computer circuit, and quantum-limited amplifiers. By optimizing the fabrication process, especially, the conductive layer during the electron beam lithography process, Al/AlOx/Al junctions of sizes ranging from 0.0169 to 0.04 µm2 on sapphire substrates were prepared. The relative standard deviation of room temperature resistances (RN) of these junctions is better than 1.7% on 15 mm×15 mm chips, and better than 2.66% on 2 inch wafers, which is the highest uniformity on sapphire substrates has been reported. The junctions are robust and stable in resistances as temperature changes. The resistances increase by the ratio of 9.73% relative to RN as the temperature ramp down to 4K, and restore their initial values in the reverse process as the temperature ramps back to RT. After being stored in a nitrogen cabinet for 100 days, the resistance of the junctions changed by1.16% in average. The demonstration of uniform and stable Josephson junctions in large area paves the way for the fabrication of superconducting chip of hundreds of qubits on sapphire substrates.