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The Japan Society of Applied Physics

Evaluation of the operating margins of contactless signal transfer circuits for serially biased SFQ circuits

Kyosuke Sano, Yutaka Abe, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Feb 3, 2017• 0 citations
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Development of Pulse Transfer Circuits for Serially Biased SFQ Circuits Using the Nb 9-Layer 1-μm\mu\hbox{m}μm Process
Serial biasing is a promising technology to reduce the total bias current of single flux quantum (SFQ) circuits. In this technique, each circuit block is placed on separated floating ground planes and biased serially. In this study, we developed a new coupling structure of SFQ pulse transfer circuits between the different ground planes using the Nb 9-layer ISTEC advanced process (ADP2.3). By using thick insulating and shielding layers, the pulse transfer circuit became robust to external magnetic fields with enough bias margins. The high-speed operation of serially biased SFQ circuits was demonstrated by on-chip high-speed tests.
Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, a novel design method that enables a wide operating margin at a high operating frequency has been investigated. The proposed circuits incorporate an additional bias feeding line in addition to the conventional bias feeding lines of the conventional Josephson transmission lines (JTLs) and can control the dependence of signal propagation time on the bias voltage. We have shown experimentally that in our proposed JTLs, the signal propagation time becomes more sensitive to the bias voltage. Timing errors can be avoided by inserting proposed JTL cells in the critical data path of the SFQ digital circuits. Circuit simulation results indicate that the operating margin of a bit-serial SFQ full adder, designed assuming the 2.5 kA/cm2Nb process, can be improved by 15% compared with the conventional design at a frequency of 20 GHz by employing our novel design method.
Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. The operating margin of an SFQ logic circuit generally decreases with an increase in the operating frequency because of the timing error in the low-bias region caused by the difference in bias dependence of the signal-propagation delay between the data and clock lines. We proposed an improvement in the operating margin by controlling the dependence of the signal-propagation time on the bias voltage. In the present study, we investigated a new optimization method for an SFQ logic gate. We developed a new circuit parameter optimizer, which takes into account not only the bias margin but also the dependence of the signal-propagation delay on the bias voltage. We defined an appropriate evaluation function for the optimization. From the result of the optimization using the defined evaluation function, we designed and demonstrated an SFQ AND gate optimized using the new optimizer.