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IEEE Transactions on Applied Superconductivity

Development of Pulse Transfer Circuits for Serially Biased SFQ Circuits Using the Nb 9-Layer 1-$\mu\hbox{m}$ Process

Kei Ehara, Akitomo Takahashi, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Dec 11, 2012• 10 citations
Publisher

Abstract

Serial biasing is a promising technology to reduce the total bias current of single flux quantum (SFQ) circuits. In this technique, each circuit block is placed on separated floating ground planes and biased serially. In this study, we developed a new coupling structure of SFQ pulse transfer circuits between the different ground planes using the Nb 9-layer ISTEC advanced process (ADP2.3). By using thick insulating and shielding layers, the pulse transfer circuit became robust to external magnetic fields with enough bias margins. The high-speed operation of serially biased SFQ circuits was demonstrated by on-chip high-speed tests.

DOI
10.1109/tasc.2012.2233535

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Development of Pulse Transfer Circuits for Serially Biased SFQ Circuits Using the Nb 9-Layer 1-μm\mu\hbox{m}μm Process
Serial biasing is a promising technology to reduce the total bias current of single flux quantum (SFQ) circuits. In this technique, each circuit block is placed on separated floating ground planes and biased serially. In this study, we developed a new coupling structure of SFQ pulse transfer circuits between the different ground planes using the Nb 9-layer ISTEC advanced process (ADP2.3). By using thick insulating and shielding layers, the pulse transfer circuit became robust to external magnetic fields with enough bias margins. The high-speed operation of serially biased SFQ circuits was demonstrated by on-chip high-speed tests.
The practical implementation of RSFQ technology in most digital electronics application areas requires much more complexity than the presently developed circuits. There are two important issues in building large-scale RSFQ circuits: 1) the recycling of the bias currents and 2) the transfer of SFQ pulses between circuits located far apart. RSFQ circuits are well known to operate with DC current bias. Even though the DC current biasing is more forgiving than the problematic AC biasing, it can still be a big concern when the circuit size becomes large. Dramatic reduction of the total bias current can be achieved by biasing several RSFQ circuits in series, where each circuit is positioned on a separate ground plane. In this work, we have used magnetically coupled Josephson transmission lines as inputs and outputs of an isolated shift register to show the feasibility of using the concept of serial biasing in current recycling. The circuit was simulated, fabricated with Nb technology, and tested at a temperature of 4.2 K. Test results show that SFQ pulses were transferred into the shift register built on a separate ground plane, clocked through it, and sent out back to the circuit on the original ground plane. We also studied on how to transfer SFQ pulses over an extended length, an important issue in building large RSFQ circuits. We have designed the circuits to test our microstrip line and multichip module approaches. We designed, optimized, fabricated and tested the circuits. Test results show that SFQ pulses can be successfully transmitted over an extensive distance in a chip and between chips.
An increase in bias currents supplied to single-flux-quantum (SFQ) circuits is a rising problem in building large-scale integrated SFQ circuits, because the magnetic fields generated by bias currents and ground return currents affect the circuit operation. Current recycling technique, which can drastically reduce the total bias current of SFQ circuits, is expected to be a very effective solution for large-scale SFQ circuits. To realize the current recycling technique, signal transmission between SFQ logic circuits located on different ground planes is required. Two types of inductively coupled pulse transfer circuits were examined in this study. One is composed of a simple JTL driver and a DC-SQUID receiver whose junctions are slightly under-damped to enhance the magnetic sensitivity of the SQUID. The other circuit is composed of an SFQ driver based on a delay flip-flop (DFF) and a SQUID receiver. The advantage of the DFF-based circuit is that the coupling time between the driver and the receiver can be increased to ensure appropriate switching in the receiver junction. Two types of transfer circuits were implemented using the SRL 2.5 kA/cm2Nb process and their correct operation was experimentally confirmed. Circuit structures for effective coupling of the SFQ pulse transfer were also investigated. It was shown that a ground plane boundary should be separated from a ground plane hole underneath coupling inductors to obtain high coupling factors.
As single flux quantum (SFQ) circuit complexities scale, larger bias currents are required. The large current produces excessive heat and greatly complicates the design process. Current recycling offers a solution by reducing the required bias current through serially biased circuit blocks. Serial biasing is typically achieved in homogeneous SFQ systems where similar bias currents are required in similar circuits. Each of these homogeneous circuits is often placed on different ground planes and serially biased to reuse the bias currents. To address heterogeneous circuits with varying bias current requirements, a novel serial biasing technique is proposed. An interface between the ground planes with unequal bias current is presented that exhibits a current balancing capability. The interface supplies additional current before passing the current to the next ground plane. The ground planes are arranged in ascending order of bias current to manage the complexity of these heterogeneous circuits. Using a one bit SFQ full adder as an example, the proposed approach demonstrates several key benefits: a 49% reduction in the number of driver-receiver pairs, a 6.5% reduction in power dissipation, and a 35% reduction in bias current across a heterogeneous SFQ circuit placed on three isolated ground planes. The performance, bias current margins, and methods for current reduction are also discussed, showcasing the effectiveness of current recycling in improving the efficiency of complex heterogeneous SFQ systems.
Large-scale SFQ integrated circuits require a large amount of dc-bias current. The magnetic fields induced by the dc-bias currents and the return currents flowing in a ground plane have a great influence on the performance of SFQ circuits. As an approach to reduce the influence, the dc-power (DCP) layer placed under a ground plane is newly introduced in SRL advanced Nb process. We have experimentally evaluated the effects of the DCP layer using SQUIDs and large-scale Josephson transmission line (JTL) circuits with more than 10,000 junctions. The SQUIDs showed that there was small magnetic flux coupling between the DCP lines and themselves and that the coupled flux was enhanced by the return current. The coupled flux decreased with increasing line width of the DCP lines and with increasing distance from the centerlines of them. In the large-scale JTL tests, the cells with DCP patterns showed wider operating margins than the CONNECT OPEN cells with partial magnetic shielding of bias current lines. The test results also showed that a line shape along the periphery of a cell was more effective than a plane shape within a cell as a DCP layer pattern for bias current feeds.
100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm2{\rm kA/cm}^{2}kA/cm2 Niobium Process
This paper reports the design and test results of a single-flux-quantum (SFQ) bit-serial adder, which we designed with a target-clock frequency of 100 GHz, to investigate several techniques for producing ultra-high-speed computations using SFQ circuits. The bit-serial adder was designed based on a new cell library developed for the ISTEC Advanced Process, where the critical current density and McCumber-Stewart parameters of Josephson junctions were increased to 10 kA/cm2and 2.0, respectively, to obtain higher operating frequencies. In addition, we adopted a circuit-design technique based on state transitions excluding a feedback loop in a typical bit-serial adder, and redesigned the NOR gate with the McCumber-Stewart parameter increased to 4.0 to improve performance. As a result, we experimentally obtained a sufficient dc bias margin of ±18% from low frequencies to 60 GHz, and verified the correctness of operations up to 93 GHz. We also demonstrated that the introduction of a higher bias voltage or large inductors in series with bias resistors is effective for achieving faster operation.
Chip-to-chip propagation of a single flux quantum (SFQ) pulse has been demonstrated using an active multichip module (MCM) technique in which active transmitters and receivers are integrated on an MCM substrate as well as on a chip. A chip-to-chip SFQ transfer circuit has been designed and implemented by a standard Nb-trilayer process and solder-bumped flip-chip technology. The correct operation of the circuit has been confirmed by low-frequency testing. Experimental margins for the global factor for bias currents have been as large as /spl plusmn/33%.