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IEICE Technical Report; IEICE Tech. Rep.

Design of Circuits Controlling Dependence of Signal Propagation Time on Bias Voltage for Expanding the Operating Margin of SFQ Circuits

Mikio Otsubo, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Jul 12, 2012• 0 citations
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Improvement of Operating Margin of SFQ Circuits by Controlling Dependence of Signal Propagation Time on Bias Voltage

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Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, a novel design method that enables a wide operating margin at a high operating frequency has been investigated. The proposed circuits incorporate an additional bias feeding line in addition to the conventional bias feeding lines of the conventional Josephson transmission lines (JTLs) and can control the dependence of signal propagation time on the bias voltage. We have shown experimentally that in our proposed JTLs, the signal propagation time becomes more sensitive to the bias voltage. Timing errors can be avoided by inserting proposed JTL cells in the critical data path of the SFQ digital circuits. Circuit simulation results indicate that the operating margin of a bit-serial SFQ full adder, designed assuming the 2.5 kA/cm2Nb process, can be improved by 15% compared with the conventional design at a frequency of 20 GHz by employing our novel design method.

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Optimization of SFQ Logic Gate Considering Dependence of its Signal Propagation Delay on the Bias Voltage

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Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. The operating margin of an SFQ logic circuit generally decreases with an increase in the operating frequency because of the timing error in the low-bias region caused by the difference in bias dependence of the signal-propagation delay between the data and clock lines. We proposed an improvement in the operating margin by controlling the dependence of the signal-propagation time on the bias voltage. In the present study, we investigated a new optimization method for an SFQ logic gate. We developed a new circuit parameter optimizer, which takes into account not only the bias margin but also the dependence of the signal-propagation delay on the bias voltage. We defined an appropriate evaluation function for the optimization. From the result of the optimization using the defined evaluation function, we designed and demonstrated an SFQ AND gate optimized using the new optimizer.

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Suzuki Stack Circuit With Differential Output

Yerzhan Mustafa, Selçuk Köse

Suzuki stack circuits, a type of latching high-voltage driver circuit, are widely used in Josephson–CMOS hybrid memories. The existing Suzuki stack designs utilize only single-ended signaling when connected to a CMOS amplifier. In this article, a Suzuki stack circuit with a differential output is proposed by producing both the positive and negative output voltages. The negative output voltage is produced by using a negative biasing network and a negative single-flux quantum (SFQ) input pulse, which is generated by the proposed positive-to-negative SFQ converter. As compared to a conventional single-ended Suzuki stack circuit, the proposed differential design can provide two times higher output voltage swing and better immunity to noise without degrading the operating margins. Potential advantages and drawbacks of the proposed circuit are explored in this article.

IEEE Transactions on Applied Superconductivity•Dec 21, 2022•15 citations
Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, a novel design method that enables a wide operating margin at a high operating frequency has been investigated. The proposed circuits incorporate an additional bias feeding line in addition to the conventional bias feeding lines of the conventional Josephson transmission lines (JTLs) and can control the dependence of signal propagation time on the bias voltage. We have shown experimentally that in our proposed JTLs, the signal propagation time becomes more sensitive to the bias voltage. Timing errors can be avoided by inserting proposed JTL cells in the critical data path of the SFQ digital circuits. Circuit simulation results indicate that the operating margin of a bit-serial SFQ full adder, designed assuming the 2.5 kA/cm2Nb process, can be improved by 15% compared with the conventional design at a frequency of 20 GHz by employing our novel design method.
Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. The operating margin of an SFQ logic circuit generally decreases with an increase in the operating frequency because of the timing error in the low-bias region caused by the difference in bias dependence of the signal-propagation delay between the data and clock lines. We proposed an improvement in the operating margin by controlling the dependence of the signal-propagation time on the bias voltage. In the present study, we investigated a new optimization method for an SFQ logic gate. We developed a new circuit parameter optimizer, which takes into account not only the bias margin but also the dependence of the signal-propagation delay on the bias voltage. We defined an appropriate evaluation function for the optimization. From the result of the optimization using the defined evaluation function, we designed and demonstrated an SFQ AND gate optimized using the new optimizer.
Suzuki stack circuits, a type of latching high-voltage driver circuit, are widely used in Josephson–CMOS hybrid memories. The existing Suzuki stack designs utilize only single-ended signaling when connected to a CMOS amplifier. In this article, a Suzuki stack circuit with a differential output is proposed by producing both the positive and negative output voltages. The negative output voltage is produced by using a negative biasing network and a negative single-flux quantum (SFQ) input pulse, which is generated by the proposed positive-to-negative SFQ converter. As compared to a conventional single-ended Suzuki stack circuit, the proposed differential design can provide two times higher output voltage swing and better immunity to noise without degrading the operating margins. Potential advantages and drawbacks of the proposed circuit are explored in this article.