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IEICE Technical Report; IEICE Tech. Rep.

Design and simulation of high temperature superconductive Single-Flux-Quantum circuit on ground plane

Kazuo Saitoh, Futoshi Furuta

Published Jul 20, 2005• 0 citations
OpenAlex

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We have investigated the flux state in high- and low- T c SFQ circuits having superconducting ground planes with moats by a scanning SQUID microscope (SSM) system. Observation of YBa 2 Cu 3 O y (YBCO) sampler circuits having superconducting ground planes with 5 µm-wide moats confirmed that magnetic flux was excluded from the moat-surrounded area including ramp-edge Josephson junctions. The threshold value for complete flux exclusion was about 0.8 µT slightly depending on chips, which can be achieved readily with dual μ-metal magnetic shielding. Moreover, we have observed the flux state in Nb multilayer structures having a superconducting ground plane with 4 µm wide moats, which was designed and fabricated using the CONNECT cell library. It was confirmed that magnetic flux was trapped selectively into moats with appropriate configuration, which were fabricated within each 40 µm × 40 µm unit cell.

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K. Fujiwara, Shuichi Nagasawa, Y. Hashimoto +7 more

One of the most important obstacles to realize high-end single-flux quantum (SFQ) digital circuits is how to eliminate the effects of trapped magnetic flux. In this study, we investigated various moat structures for multi-layer devices with multiple ground planes to determine which moat configuration was most suitable for a cell library. We designed various test circuits with different moat structures and evaluated their effectiveness by measuring the I-V characteristics of superconducting quantum interface device (SQUID) test circuits. Tests were carried out at several milli-gauss to evaluate the moats. We concluded that the most suitable moat configuration for a multi-layer device structure was obtained by surrounding the SFQ circuits with basic via moats in all ground layers of bias ports with ground contacts and by using narrow rectangular moats in only the main ground plane.

IEEE Transactions on Applied Superconductivity•Jun 1, 2009•15 citations

Low error operation of high T_c superconducting single-flux quantum simple circuits

T. S. Hahn, J H Park, J.H. Kang

低温工学・超電導学会講演概要集 = Meetings of Cryogenics and Superconductivity•Nov 23, 2001•0 citations
We have investigated the flux state in high- and low- T c SFQ circuits having superconducting ground planes with moats by a scanning SQUID microscope (SSM) system. Observation of YBa 2 Cu 3 O y (YBCO) sampler circuits having superconducting ground planes with 5 µm-wide moats confirmed that magnetic flux was excluded from the moat-surrounded area including ramp-edge Josephson junctions. The threshold value for complete flux exclusion was about 0.8 µT slightly depending on chips, which can be achieved readily with dual μ-metal magnetic shielding. Moreover, we have observed the flux state in Nb multilayer structures having a superconducting ground plane with 4 µm wide moats, which was designed and fabricated using the CONNECT cell library. It was confirmed that magnetic flux was trapped selectively into moats with appropriate configuration, which were fabricated within each 40 µm × 40 µm unit cell.
We suggest a new design of rapid single flux quantum (RSFQ) logic circuits which is based on a single superconducting layer and does not require a superconducting ground plane. Small inductances of about 10 pH, obligatory for RSFQ circuits, are formed as narrow slits of widths comparable to the London penetration depth (≂0.15 μm). The design allows us to decrease the geometric size of the RSFQ cell. Test circuits with YBaCuO grain boundary junctions on asymmetric 32° Y– ZrO2 bicrystals were used to measure the slit inductance per unit length and the mutual inductance of neighboring slits. A typical inductance of a 0.4 μm slit was found to be 0.7–0.8 pH/μm.
One of the most important obstacles to realize high-end single-flux quantum (SFQ) digital circuits is how to eliminate the effects of trapped magnetic flux. In this study, we investigated various moat structures for multi-layer devices with multiple ground planes to determine which moat configuration was most suitable for a cell library. We designed various test circuits with different moat structures and evaluated their effectiveness by measuring the I-V characteristics of superconducting quantum interface device (SQUID) test circuits. Tests were carried out at several milli-gauss to evaluate the moats. We concluded that the most suitable moat configuration for a multi-layer device structure was obtained by surrounding the SFQ circuits with basic via moats in all ground layers of bias ports with ground contacts and by using narrow rectangular moats in only the main ground plane.