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IEEE Transactions on Applied Superconductivity

Research on Effective Moat Configuration for Nb Multi-Layer Device Structure

K. Fujiwara, Shuichi Nagasawa, Y. Hashimoto, M. Hidaka, Nobuyuki Yoshikawa, Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi

Published Jun 1, 2009• 15 citations
Publisher

Abstract

One of the most important obstacles to realize high-end single-flux quantum (SFQ) digital circuits is how to eliminate the effects of trapped magnetic flux. In this study, we investigated various moat structures for multi-layer devices with multiple ground planes to determine which moat configuration was most suitable for a cell library. We designed various test circuits with different moat structures and evaluated their effectiveness by measuring the I-V characteristics of superconducting quantum interface device (SQUID) test circuits. Tests were carried out at several milli-gauss to evaluate the moats. We concluded that the most suitable moat configuration for a multi-layer device structure was obtained by surrounding the SFQ circuits with basic via moats in all ground layers of bias ports with ground contacts and by using narrow rectangular moats in only the main ground plane.

DOI
10.1109/tasc.2009.2018545

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One of the most important obstacles to realize high-end single-flux quantum (SFQ) digital circuits is how to eliminate the effects of trapped magnetic flux. In this study, we investigated various moat structures for multi-layer devices with multiple ground planes to determine which moat configuration was most suitable for a cell library. We designed various test circuits with different moat structures and evaluated their effectiveness by measuring the I-V characteristics of superconducting quantum interface device (SQUID) test circuits. Tests were carried out at several milli-gauss to evaluate the moats. We concluded that the most suitable moat configuration for a multi-layer device structure was obtained by surrounding the SFQ circuits with basic via moats in all ground layers of bias ports with ground contacts and by using narrow rectangular moats in only the main ground plane.
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Abstract Flux trapping in superconducting integrated circuits cause circuits to operate with reduced margins, or to fail completely. Moats are used in superconducting ground planes to create low energy locations for flux trapping. Moat design and placement strategies have been presented before, and several experiments published to evaluate moat efficiency. Although fluxons can be steered to moats to prevent trapping in or near Josephson junctions or inductive interconnects, the flux in a moat couples to nearby structures and induces dc currents in superconducting loops. In this paper, we discuss a set of numerical simulation tools for flux trapping analysis, developed under the IARPA SuperTools project. These tools are used to extract compact models for magnetic flux trapped in moats, including the magnetic coupling to superconducting structures. An open-source superconducting transient simulation engine, called JoSIM, is used to simulate these compact models. To evaluate the magnetic coupling of different moat configurations, we developed a set of a flux linkage experiments. Test structures were designed for the multi-layer MIT Lincoln Laboratory SFQ5ee process that allow for flux insertion into moats of different configurations. From experimental results we measure the effects of trapped flux, in different moat structures, on SQUID parameters and use the results to validate the compact models used by our tools.
We report experimental investigations of a simple structure, called a moat, which significantly reduces the probability of flux-trapping in Josephson SQUIDs. Proper operation of Josephson logic and memory circuits requires that the SQUIDs be free of stray magnetic flux that may become trapped in the superconducting groundplane upon cooling through the critical temperature. The problem is particularly severe for so-called holey SQUIDs which rely on holes in the groundplane to obtain suitably large device inductances. Moats are rectangular channels in the groundplane surrounding the SQUID's which provide preferred sites for trapping flux, thus preventing such flux from coupling to the SQUID. We have measured the effectiveness of moats by monitoring the flux trapped in the moats and comparing it to the flux trapped in the associated SQUID as a function of applied field. The number of flux quanta in the moat is determined by measuring the shift of the threshold curve of a two-junction SQUID coupled to the moat. The data indicates that at fields on the order of a mG, moats reduce the sensitivity of holey SQUIDs to trapped flux by at least several orders of magnitude. As the chips are cooled through Tc, transient magnetic fields are produced in the metallic sample holder parts surrounding the chip by thermal-gradient-induced EMF's. The effects of such magnetic fields on the flux trapping behaviour of the SQUIDs are also reported.
We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (IC), bias current (Ibias), and inductance satisfied minimal margin requirements. Critical margins of ICand Ibiaswere then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC. The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.
Moats in superconducting ground planes are used to trap magnetic flux away from sensitive parts of superconductor integrated circuits. We simulate the effect of magnetic flux trapped in moats on the operating margins of ac-biased SFQ shift registers (ShReg) with two ground planes for various congruent moat geometries, moat sizes, locations in the ShReg cells, number and polarity of the trapped fluxons. Using inductance extractor InductEx, we extract mutual couplings between the moats and the ShReg inductors and include them in the refined netlist. Then we use JoSim to simulate the circuit operation and find the threshold ac clock amplitude above which the register starts to operate correctly. The relative change in this threshold is used to characterize the influence of flux trapping on the circuit operation. Monte-Carlo simulations are used to investigate the effect of the circuit parameter variations on the statistics of the threshold, using the standard deviation of the Josephson junction critical current and of the circuit inductance extracted from the fabrication process control monitors. The obtained distributions are compared with the independently measured distributions of the threshold amplitude for the individual cells of an ac-biased shift registers with 108,500 Josephson junctions. The results show that flux trapping in properly designed moats has a very small effect on the operation margins of the large-scale shift registers, whereas the main contribution to the cell-to-cell variation of the threshold comes from the variation of the junctions’ critical currents.