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Superconductor Science and Technology

Investigation of the flux state in single-flux-quantum circuits with moats by scanning SQUID microscope

Koji A. O. Suzuki, Hiroki Kawamura, Michitaka Maruyama, Tsunehiro Hato, Hideo Suzuki, Shinichi Yorozu, Y Kameda, Yoshihiro Ishimaru, Ken‐ichi Nakayama, H. Wakana, Seiji Adachi, Y. Tarutani, K. Tanabe

Published Mar 16, 2006• 5 citations
Publisher

Abstract

We have investigated the flux state in high- and low- T c SFQ circuits having superconducting ground planes with moats by a scanning SQUID microscope (SSM) system. Observation of YBa 2 Cu 3 O y (YBCO) sampler circuits having superconducting ground planes with 5 µm-wide moats confirmed that magnetic flux was excluded from the moat-surrounded area including ramp-edge Josephson junctions. The threshold value for complete flux exclusion was about 0.8 µT slightly depending on chips, which can be achieved readily with dual μ-metal magnetic shielding. Moreover, we have observed the flux state in Nb multilayer structures having a superconducting ground plane with 4 µm wide moats, which was designed and fabricated using the CONNECT cell library. It was confirmed that magnetic flux was trapped selectively into moats with appropriate configuration, which were fabricated within each 40 µm × 40 µm unit cell.

DOI
10.1088/0953-2048/19/5/s32

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We have investigated the flux state in high- and low- T c SFQ circuits having superconducting ground planes with moats by a scanning SQUID microscope (SSM) system. Observation of YBa 2 Cu 3 O y (YBCO) sampler circuits having superconducting ground planes with 5 µm-wide moats confirmed that magnetic flux was excluded from the moat-surrounded area including ramp-edge Josephson junctions. The threshold value for complete flux exclusion was about 0.8 µT slightly depending on chips, which can be achieved readily with dual μ-metal magnetic shielding. Moreover, we have observed the flux state in Nb multilayer structures having a superconducting ground plane with 4 µm wide moats, which was designed and fabricated using the CONNECT cell library. It was confirmed that magnetic flux was trapped selectively into moats with appropriate configuration, which were fabricated within each 40 µm × 40 µm unit cell.
One of the most important obstacles to realize high-end single-flux quantum (SFQ) digital circuits is how to eliminate the effects of trapped magnetic flux. In this study, we investigated various moat structures for multi-layer devices with multiple ground planes to determine which moat configuration was most suitable for a cell library. We designed various test circuits with different moat structures and evaluated their effectiveness by measuring the I-V characteristics of superconducting quantum interface device (SQUID) test circuits. Tests were carried out at several milli-gauss to evaluate the moats. We concluded that the most suitable moat configuration for a multi-layer device structure was obtained by surrounding the SFQ circuits with basic via moats in all ground layers of bias ports with ground contacts and by using narrow rectangular moats in only the main ground plane.
We report experimental investigations of a simple structure, called a moat, which significantly reduces the probability of flux-trapping in Josephson SQUIDs. Proper operation of Josephson logic and memory circuits requires that the SQUIDs be free of stray magnetic flux that may become trapped in the superconducting groundplane upon cooling through the critical temperature. The problem is particularly severe for so-called holey SQUIDs which rely on holes in the groundplane to obtain suitably large device inductances. Moats are rectangular channels in the groundplane surrounding the SQUID's which provide preferred sites for trapping flux, thus preventing such flux from coupling to the SQUID. We have measured the effectiveness of moats by monitoring the flux trapped in the moats and comparing it to the flux trapped in the associated SQUID as a function of applied field. The number of flux quanta in the moat is determined by measuring the shift of the threshold curve of a two-junction SQUID coupled to the moat. The data indicates that at fields on the order of a mG, moats reduce the sensitivity of holey SQUIDs to trapped flux by at least several orders of magnitude. As the chips are cooled through Tc, transient magnetic fields are produced in the metallic sample holder parts surrounding the chip by thermal-gradient-induced EMF's. The effects of such magnetic fields on the flux trapping behaviour of the SQUIDs are also reported.
Moats in superconducting ground planes are used to trap magnetic flux away from sensitive parts of superconductor integrated circuits. We simulate the effect of magnetic flux trapped in moats on the operating margins of ac-biased SFQ shift registers (ShReg) with two ground planes for various congruent moat geometries, moat sizes, locations in the ShReg cells, number and polarity of the trapped of fluxons. Using inductance extractor InductEx, we extract mutual couplings between the moats and the ShReg inductors and include them in the refined netlist. Then, we use JoSim to simulate the circuit operation and find the threshold ac clock amplitude above which the register starts to operate correctly. The relative change in this threshold is used to characterize the influence of flux trapping on the circuit operation. Monte-Carlo simulations are used to investigate the effect of the circuit parameter variations on the statistics of the threshold, using the standard deviation of the Josephson junction critical current and of the circuit inductance extracted from the fabrication process control monitors. The obtained distributions are compared with the independently measured distributions of the threshold amplitude for the individual cells of ac-biased shift registers with 108,500 Josephson junctions. The results show that flux trapping in properly designed moats have a very small effect on the operation margins of the large-scale shift registers whereas the main contribution to the cell-to-cell variation of the threshold comes from the variation of the junctions' critical currents.
Moats in superconducting ground planes are used to trap magnetic flux away from sensitive parts of superconductor integrated circuits. We simulate the effect of magnetic flux trapped in moats on the operating margins of ac-biased SFQ shift registers (ShReg) with two ground planes for various congruent moat geometries, moat sizes, locations in the ShReg cells, number and polarity of the trapped fluxons. Using inductance extractor InductEx, we extract mutual couplings between the moats and the ShReg inductors and include them in the refined netlist. Then we use JoSim to simulate the circuit operation and find the threshold ac clock amplitude above which the register starts to operate correctly. The relative change in this threshold is used to characterize the influence of flux trapping on the circuit operation. Monte-Carlo simulations are used to investigate the effect of the circuit parameter variations on the statistics of the threshold, using the standard deviation of the Josephson junction critical current and of the circuit inductance extracted from the fabrication process control monitors. The obtained distributions are compared with the independently measured distributions of the threshold amplitude for the individual cells of an ac-biased shift registers with 108,500 Josephson junctions. The results show that flux trapping in properly designed moats has a very small effect on the operation margins of the large-scale shift registers, whereas the main contribution to the cell-to-cell variation of the threshold comes from the variation of the junctions’ critical currents.
A variety of superconductor integrated circuits composed of six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm × 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers, allowing for their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, distance between moats in active ground planes (GPs), and containing up to three additional ‘dummy’ GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to ∼ 1.2 µT. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and a negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-µm-wide slit moats occupying less than 2% of the circuit area were fully operational in 100% of cooldowns, supporting the viability of a very large-scale integration of superconductor digital circuits. We have also found a strong enhancement of flux trapping outside the moats in circuits with closely spaced GPs and determined a critical distance,${{{\boldsymbol{t}}}_{\boldsymbol{c}}} \approx $0.6 µm, between them. The presence of two or more GPs spaced below thetcrendered the circuits nonoperational in 100% of cooldowns. We have measured 30 chips with over 3M JJs and determined individual cell operating margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier bit-cells in the statistical distribution of the individual cell margins, we detected about one fabrication defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.The circuits have been fabricated in the SFQ5ee fabrication process at MIT Lincoln Laboratory (MIT LL).