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IEEE Transactions on Applied Superconductivity

Active Manipulation of Trapped Flux in Nb Chip at a Single Vortex Level (2025)

Brenna Petrelli, J. Bedard, Jacob Franklin, Kyle Jackman, Lieze Schindler, Johannes A. Delport, Tessa Hall, Paul Rossouw, Coenrad Johann Fourie, Daniel T. Yohannes, Oleg A. Mukhanov, Ilya Sochnikov

Published Mar 24, 2026• 0 citations
Publisher

Abstract

Trapped magnetic flux has been a long-standing problem in superconducting digital and quantum circuits, significantly affecting their reliability and limiting practical applications. Mitigation techniques like integrating moat structures into circuit layouts and increasing magnetic shielding have been in use to improve the probability of an accurate circuit operation. However, none of the methods can reliably and deterministically achieve the desired flux-free state of superconducting circuits. Active flux management can potentially solve this problem by the removal of the trapped flux from the relevant circuit areas on a chip. Here, we report numerical modelling and experimental scanning SQUID imaging results showing flux manipulation on the single vortex level using a network of pulsed electric lines in a test superconducting single layer circuit. We demonstrate the effect of vortex sweeping in areas with control lines as well as sweeping of vortices into moats via Lorentz force mechanism. This method can potentially be expanded to larger and more sophisticated digital and quantum chips.

DOI
10.1109/tasc.2026.3677318

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Trapped magnetic flux has been a long-standing problem in superconducting digital and quantum circuits, significantly affecting their reliability and limiting practical applications. Mitigation techniques like integrating moat structures into circuit layouts and increasing magnetic shielding have been in use to improve the probability of an accurate circuit operation. However, none of the methods can reliably and deterministically achieve the desired flux-free state of superconducting circuits. Active flux management can potentially solve this problem by the removal of the trapped flux from the relevant circuit areas on a chip. Here, we report numerical modelling and experimental scanning SQUID imaging results showing flux manipulation on the single vortex level using a network of pulsed electric lines in a test superconducting single layer circuit. We demonstrate the effect of vortex sweeping in areas with control lines as well as sweeping of vortices into moats via Lorentz force mechanism. This method can potentially be expanded to larger and more sophisticated digital and quantum chips.
Superconductor digital electronics and quantum computing with superconducting qubits are promising next-generation computing technologies. When cooled down or operated in the presence of a nonzero background magnetic field BrB_rBr​, superconducting thin films comprising the circuits can trap magnetic vortices that can degrade circuit or qubit performance. In this work, we report a practical solution for eliminating flux trapped during cooldown in ambient magnetic fields, Br≤60B_r\leq 60Br​≤60 $\upmu$T, based on controlled local thermal gradients and moats, etched holes in the superconducting films of the circuit. Thermal gradients created by integrated on-chip resistive heaters move vortices towards the moats, where they become trapped away from circuitry regions and pinning sites. Using magnetic imaging and electrical circuit readout, we demonstrate that this approach is capable of removing magnetic flux trapped during field cooling and magnetic flux nucleated by circuit operation. If used in an environment with basic magnetic shielding, this solution is capable of suppressing all magnetic flux in a large-scale circuit, overcoming one of the long-standing challenges preventing high-performance scalable computing using superconductors.
We have investigated the flux state in high- and low- T c SFQ circuits having superconducting ground planes with moats by a scanning SQUID microscope (SSM) system. Observation of YBa 2 Cu 3 O y (YBCO) sampler circuits having superconducting ground planes with 5 µm-wide moats confirmed that magnetic flux was excluded from the moat-surrounded area including ramp-edge Josephson junctions. The threshold value for complete flux exclusion was about 0.8 µT slightly depending on chips, which can be achieved readily with dual μ-metal magnetic shielding. Moreover, we have observed the flux state in Nb multilayer structures having a superconducting ground plane with 4 µm wide moats, which was designed and fabricated using the CONNECT cell library. It was confirmed that magnetic flux was trapped selectively into moats with appropriate configuration, which were fabricated within each 40 µm × 40 µm unit cell.
The influence of a trapped flux quantum in a superconducting ground plane hole, called a moat, on superconducting circuit operation was analyzed. We devised a calculation model to estimate the magnetic flux threading a signal line of a superconducting integrated circuit by the trapped flux quantum in a moat placed near the signal line, by using a conventional inductance extraction tool. Assuming one flux quantum trapped in the moat, the dependence of the magnetic flux threading the signal line on the distance between the moat and the signal line were calculated. We measured the flux linkage by measuring the modulation of the I-V characteristic of a dc-SQUID with a moat near the SQUID implemented by using the 2.5 kA/cm2Nb standard process. The measured flux linkage agrees well with the analysis results using the devised calculation model. When the distance between the 1 μm × 10 μm moat and the SQUID, the signal line size of which corresponds to the typical inductance of an adiabatic flux quantum parametron (AQFP) is 1 μm and one flux quantum is trapped in the moat, the measured magnetic flux linkage threads the signal line was approximately 1.2% of the flux quantum. This flux linkage induces approximately 4% deterioration of the device margin of the AQFP. The devised calculation model and experimental results provide useful information for designing highly integrated future superconducting integrated circuits.
Abstract Flux trapping in superconducting integrated circuits cause circuits to operate with reduced margins, or to fail completely. Moats are used in superconducting ground planes to create low energy locations for flux trapping. Moat design and placement strategies have been presented before, and several experiments published to evaluate moat efficiency. Although fluxons can be steered to moats to prevent trapping in or near Josephson junctions or inductive interconnects, the flux in a moat couples to nearby structures and induces dc currents in superconducting loops. In this paper, we discuss a set of numerical simulation tools for flux trapping analysis, developed under the IARPA SuperTools project. These tools are used to extract compact models for magnetic flux trapped in moats, including the magnetic coupling to superconducting structures. An open-source superconducting transient simulation engine, called JoSIM, is used to simulate these compact models. To evaluate the magnetic coupling of different moat configurations, we developed a set of a flux linkage experiments. Test structures were designed for the multi-layer MIT Lincoln Laboratory SFQ5ee process that allow for flux insertion into moats of different configurations. From experimental results we measure the effects of trapped flux, in different moat structures, on SQUID parameters and use the results to validate the compact models used by our tools.
We report experimental investigations of a simple structure, called a moat, which significantly reduces the probability of flux-trapping in Josephson SQUIDs. Proper operation of Josephson logic and memory circuits requires that the SQUIDs be free of stray magnetic flux that may become trapped in the superconducting groundplane upon cooling through the critical temperature. The problem is particularly severe for so-called holey SQUIDs which rely on holes in the groundplane to obtain suitably large device inductances. Moats are rectangular channels in the groundplane surrounding the SQUID's which provide preferred sites for trapping flux, thus preventing such flux from coupling to the SQUID. We have measured the effectiveness of moats by monitoring the flux trapped in the moats and comparing it to the flux trapped in the associated SQUID as a function of applied field. The number of flux quanta in the moat is determined by measuring the shift of the threshold curve of a two-junction SQUID coupled to the moat. The data indicates that at fields on the order of a mG, moats reduce the sensitivity of holey SQUIDs to trapped flux by at least several orders of magnitude. As the chips are cooled through Tc, transient magnetic fields are produced in the metallic sample holder parts surrounding the chip by thermal-gradient-induced EMF's. The effects of such magnetic fields on the flux trapping behaviour of the SQUIDs are also reported.
One of the most important obstacles to realize high-end single-flux quantum (SFQ) digital circuits is how to eliminate the effects of trapped magnetic flux. In this study, we investigated various moat structures for multi-layer devices with multiple ground planes to determine which moat configuration was most suitable for a cell library. We designed various test circuits with different moat structures and evaluated their effectiveness by measuring the I-V characteristics of superconducting quantum interface device (SQUID) test circuits. Tests were carried out at several milli-gauss to evaluate the moats. We concluded that the most suitable moat configuration for a multi-layer device structure was obtained by surrounding the SFQ circuits with basic via moats in all ground layers of bias ports with ground contacts and by using narrow rectangular moats in only the main ground plane.