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低温工学・超電導学会講演概要集 = Meetings of Cryogenics and Superconductivity

Low error operation of high T_c superconducting single-flux quantum simple circuits

T. S. Hahn, J H Park, J.H. Kang

Published Nov 23, 2001• 0 citations
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The thermally induced bit error rate of a rapid single flux quantum logic circuit is theoretically examined using the Fokker–Planck equation. The error rate versus design parameters of a high Tc dc/single flux quantum converter is derived. In comparison with other design methodologies, a vanishingly small error rate at optimal parameters can be achieved.

Applied Physics Letters•Feb 26, 2001•11 citations
A 3 bit single flux quantum (SFQ) shift register based on high-Tc bicrystal Josephson junctions has been designed, fabricated, and experimentally tested. The circuit consists of 26 bicrystal Josephson junctions and includes the shift register itself, two dc-SFQ converters, one readout superconducting quantum interference device, serving as a SFQ-dc converter, and three Josephson transmission lines. The correct operation of all circuit components has been demonstrated by low frequency testing at a temperature of 50 K.
Superconducting single flux quantum (SFQ) circuits are promising for digital signal processing systems. However, conventional binary arithmetic does not take full advantage of the fundamental properties of SFQ circuits. The residue number system (RNS) is intrinsically more compatible with single flux quantum circuits, and provides the advantage of modularity, parallelism, carry-free structure, simple multiplication and fault tolerance. We designed a one-decimal-digit adder to demonstrate this new technology. The exclusive use of simple and robust Josephson shift registers creates large margins, simple circuit architecture and high throughput. These attributes are important for state-of-the-art superconducting technology, and are especially crucial for high temperature superconducting digital circuits. We designed, simulated and extensively optimized a mod 5 adder and its subcells. We laid out the circuits and had them fabricated. We tested the low speed functionality of these circuits using a manual test setup and a LabVIEW automated test setup. All the subcell experimental results show decent operation margins and good consistency with the simulation results, and demonstration of the entire mod 5 adder should be straightforward. An SFQ RNS 8-bit multiplier is proposed. Comparing to superconducting binary bit-serial and bit-parallel 8-bit multipliers, it shows an advantage in design simplicity, operation margins, error rate and throughput, along with its unique feature of simple fault tolerance. We thus believe that RNS, rather than binary, could be the natural language for superconducting digital electronics, especially in the application of digital signal processors.