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Journal of Physics Conference Series

Run-to-Run Yield Evaluation of Improved Nb 9-layer Advanced Process using Single Flux Quantum Shift Register Chip with 68,990 Josephson Junctions

Shuichi Nagasawa, Mutsuo Hidaka

Published Jul 1, 2017• 11 citations
Publisher

Abstract

We have improved an Nb 9-layer advanced process (ADP2) using a plasma-enhanced chemical vapor deposition (PECVD) SiO 2 insulator. We could solve the problems due to the surface profile of the PECVD SiO 2 by adding an ion-milling process. The reliability of the ADP2 was evaluated by the operating yield of the SFQ shift registers (SRs). The SRs with six different bit sizes from 16 to 2560 were designed to evaluate the circuit size dependency of their yields. The total number of SRs is 16, and the total number of junctions per chip is 68,990. By introducing the PECVD SiO 2 insulator, we could obtain a high operating yield of more than 80% even for large-scale 2560-bit shift registers with more than 10,000 junctions. Moreover, we could obtain nine perfect chips (in which all the SRs in the chip functioned) out of 26 measured chips fabricated using the PECVD SiO 2 . From these results, we believe that the fabrication yield of the ADP2 is at a level of 100,000 Josephson junction circuits.

DOI
10.1088/1742-6596/871/1/012065

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We have improved an Nb 9-layer advanced process (ADP2) using a plasma-enhanced chemical vapor deposition (PECVD) SiO 2 insulator. We could solve the problems due to the surface profile of the PECVD SiO 2 by adding an ion-milling process. The reliability of the ADP2 was evaluated by the operating yield of the SFQ shift registers (SRs). The SRs with six different bit sizes from 16 to 2560 were designed to evaluate the circuit size dependency of their yields. The total number of SRs is 16, and the total number of junctions per chip is 68,990. By introducing the PECVD SiO 2 insulator, we could obtain a high operating yield of more than 80% even for large-scale 2560-bit shift registers with more than 10,000 junctions. Moreover, we could obtain nine perfect chips (in which all the SRs in the chip functioned) out of 26 measured chips fabricated using the PECVD SiO 2 . From these results, we believe that the fabrication yield of the ADP2 is at a level of 100,000 Josephson junction circuits.
We are investigating device yield in our Nb-nine-layer fabrication process for single-flux-quantum (SFQ) circuits, in which the critical current density of the Nb/AlOx/ Nb Josephson junction (JJ) is 10 kA/cm2and the minimum JJ size is 1 μm2. We fabricated several shift registers (SRs) with different sizes that exhibit bit capacities from 16 to 2560 bits on a chip on many wafers. The SR yields correlate roughly with process defect test results using diagnostic chips, which are included in all wafers and consist of various diagnostic patterns such as for interlayer and intralayer insulations. When the defect number was above a certain level, the SR yield drastically degraded. The other reason of SR yield degradation is poor size uniformity of JJ patterns. The JJ pattern resolutions using our i-line stepper depend on the several-μm-level flatness of wafers. All SRs on a chip consisting of 68 990 JJs operated correctly. We obtained both “good” and “poor” chips without intentional changes of process conditions. The “poor” chip was strongly affected by magnetic flux traps. We believe that determining the cause of this difference is key to fabricating SFQ circuits consisting of 100 000 or more JJs.
We describe the recent progress on a Nb nine-layer fabrication process for large-scale single flux quantum (SFQ) circuits. A device fabricated in this process is composed of an active layer including Josephson junctions (JJ) at the top, passive transmission line (PTL) layers in the middle, and a DC power layer at the bottom. We describe the process conditions and the fabrication equipment. We use both diagnostic chips and shift register (SR) chips to improve the fabrication process. The diagnostic chip was designed to evaluate the characteristics of basic elements such as junctions, contacts, resisters, and wiring, in addition to their defect evaluations. The SR chip was designed to evaluate defects depending on the size of the SFQ circuits. The results of a long-term evaluation of the diagnostic and SR chips showed that there was fairly good correlation between the defects of the diagnostic chips and yields of the SRs. We could obtain a yield of 100% for SRs including 70,000JJs. These results show that considerable progress has been made in reducing the number of defects and improving reliability.
We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 1×1μm, a line width of 0.8μm, a JJ critical current density of 10kA/cm2, a 2.4Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.
The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a Jc = 2.5 kA cm−2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a Jc = 10 kA cm−2, nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a Jc = 40 kA cm−2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.
A simple and robust process for fabricating low-T/sub c/ Josephson junction integrated circuits has been developed. The process is designed around the Nb/Al/sub 2/O/sub 3/-Al/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD equipment yields a high deposition rate at moderate substrate temperatures. No degradation of the junction characteristics due to these depositions is seen. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44*10/sup -4/. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. A variety of simple circuits using this process technology have been fabricated and tested. More complex circuits are currently under development.
Abstract We present SIMIT-Nb08, an eight-layer Nb-based fabrication process for double-active-layer single-flux-quantum (SFQ) digital circuits, aimed at overcoming the routing congestion and integration ‘density wall’ of planar SFQ designs. Both Nb/Al–AlO x /Nb JJ layers were designed with the same nominal critical current density of J c = 6 kA cm −2 , and the measured values were 6.15 and 6.26 kA cm −2 for the lower and upper JJ layers, respectively. This architecture incorporates a dual-ground-plane structure to reduce interlayer electromagnetic coupling and shield stray magnetic flux generated by bias lines. A stop-on-metal chemical mechanical polishing module was implemented to provide a controlled dielectric thickness and a planar surface for upper-layer device fabrication. We validate a double-layer SFQ logic cell library with wide DC bias margins on both layers, and demonstrate ultra-high-speed dynamic operation via a toggle flip-flop-based frequency-divider test exceeding 100 GHz. In addition, the process and cross-layer interconnect reliability are demonstrated by functional operation of a cross-layer one-bit full adder and an eight-bit shift register (SR), where the SR exhibits an effective junction-density improvement of ∼4× over typical single-layer implementations. Post-route benchmarking on a 320-cell SR indicates that SIMIT-Nb08 delivers substantial improvements in power, performance, and area, including a 32.2% reduction in area, a 25.0% increase in maximum operating frequency ( f max ), and a 65.3% reduction in estimated power compared with SIMIT-Nb03 (29.9%, 6.3%, and 62.5%, respectively, compared with SIMIT-Nb04), indicating its potential for routing-constrained SFQ digital circuits.