Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEICE Transactions on Electronics

Improvements in Fabrication Process for Nb-Based Single Flux Quantum Circuits in Japan

Mutsuo Hidaka, Shuichi Nagasawa, K. Hinode, T. SATOH

Published Mar 1, 2008• 34 citations
Publisher

Abstract

We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 1×1μm, a line width of 0.8μm, a JJ critical current density of 10kA/cm2, a 2.4Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.

DOI
10.1093/ietele/e91-c.3.318

Related papers

Current status and future prospect of the Nb-based fabrication process for single flux quantum circuits

Mutsuo Hidaka, Shuichi Nagasawa, T. Satoh +2 more

The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a Jc = 2.5 kA cm−2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a Jc = 10 kA cm−2, nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a Jc = 40 kA cm−2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.

Superconductor Science and Technology•Feb 15, 2006•62 citations

Device Yield in Nb-Nine-Layer Circuit Fabrication Process

Mutsuo Hidaka, Shuichi Nagasawa, K. Hinode +1 more

We are investigating device yield in our Nb-nine-layer fabrication process for single-flux-quantum (SFQ) circuits, in which the critical current density of the Nb/AlOx/ Nb Josephson junction (JJ) is 10 kA/cm2and the minimum JJ size is 1 μm2. We fabricated several shift registers (SRs) with different sizes that exhibit bit capacities from 16 to 2560 bits on a chip on many wafers. The SR yields correlate roughly with process defect test results using diagnostic chips, which are included in all wafers and consist of various diagnostic patterns such as for interlayer and intralayer insulations. When the defect number was above a certain level, the SR yield drastically degraded. The other reason of SR yield degradation is poor size uniformity of JJ patterns. The JJ pattern resolutions using our i-line stepper depend on the several-μm-level flatness of wafers. All SRs on a chip consisting of 68 990 JJs operated correctly. We obtained both “good” and “poor” chips without intentional changes of process conditions. The “poor” chip was strongly affected by magnetic flux traps. We believe that determining the cause of this difference is key to fabricating SFQ circuits consisting of 100 000 or more JJs.

IEEE Transactions on Applied Superconductivity•Jan 1, 2013•13 citations

Fabrication Process of Planarized Multi-Layer Nb Integrated Circuits

T. Satoh, K. Hinode, Hiroyuki Akaike +3 more

To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.

IEEE Transactions on Applied Superconductivity•Jun 1, 2005•42 citations

Investigation of SFQ integrated circuits using Nb fabrication technology

Hideaki Numata, Masamitsu Tanaka, Y Kitagawa +1 more

In NEC's standard process, the minimum junction size is 2 µm and the critical current density ( J C ) is 2.5 kA cm -2 . In the process, i-line stepper lithography and reactive ion etching with SF 6 gas are used and the standard deviation ( ) of the critical current ( I C ) was 0.9% for the 2 µm junctions. This junction uniformity enables integration of more than 10M junctions if an I C variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits.

Superconductor Science and Technology•Nov 1, 1999•17 citations

High density fabrication process for single flux quantum circuits

Daniel T. Yohannes, Mario Renzullo, John A. Vivalda +6 more

We implemented, optimized, and fully tested a superconducting Josephson junction fabrication process over multiple runs tailored for integrated digital circuits that are used for control and readout of superconducting qubits operating at millikelvin temperatures. This process was optimized for highly energy efficient rapid single flux quantum (ERSFQ) circuits with critical currents reduced by a factor of ∼10 as compared to those operated at 4.2 K. Specifically, it implemented Josephson junctions with 10 μA unit critical current fabricated with 10 μA/μm2 critical current density. In order to circumvent the substantial size increase in the SFQ circuit inductors, we employed an NbN high kinetic inductance layer with 8.5 pH/sq sheet inductance. Similarly, to maintain the small size of junction resistive shunts, we used a non-superconducting PdAu alloy with 4.0 Ω/sq sheet resistance. For integration with quantum circuits in a multi-chip module, 5 and 10 μm height bump processes were also optimized. To keep the fabrication process in check, we developed and thoroughly tested a comprehensive process control monitor chip set.

arXiv:2305.07607•Applied Physics Letters•May 22, 2023•17 citations

A double-active-layer NB-based fabrication process for superconducting digital integrated circuits

Mingfan Chen, Shucheng Yang, Liliang Ying +7 more

Abstract We present SIMIT-Nb08, an eight-layer Nb-based fabrication process for double-active-layer single-flux-quantum (SFQ) digital circuits, aimed at overcoming the routing congestion and integration ‘density wall’ of planar SFQ designs. Both Nb/Al–AlO x /Nb JJ layers were designed with the same nominal critical current density of J c = 6 kA cm −2 , and the measured values were 6.15 and 6.26 kA cm −2 for the lower and upper JJ layers, respectively. This architecture incorporates a dual-ground-plane structure to reduce interlayer electromagnetic coupling and shield stray magnetic flux generated by bias lines. A stop-on-metal chemical mechanical polishing module was implemented to provide a controlled dielectric thickness and a planar surface for upper-layer device fabrication. We validate a double-layer SFQ logic cell library with wide DC bias margins on both layers, and demonstrate ultra-high-speed dynamic operation via a toggle flip-flop-based frequency-divider test exceeding 100 GHz. In addition, the process and cross-layer interconnect reliability are demonstrated by functional operation of a cross-layer one-bit full adder and an eight-bit shift register (SR), where the SR exhibits an effective junction-density improvement of ∼4× over typical single-layer implementations. Post-route benchmarking on a 320-cell SR indicates that SIMIT-Nb08 delivers substantial improvements in power, performance, and area, including a 32.2% reduction in area, a 25.0% increase in maximum operating frequency ( f max ), and a 65.3% reduction in estimated power compared with SIMIT-Nb03 (29.9%, 6.3%, and 62.5%, respectively, compared with SIMIT-Nb04), indicating its potential for routing-constrained SFQ digital circuits.

Superconductor Science and Technology•Sep 30, 2026•0 citations
We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 1×1μm, a line width of 0.8μm, a JJ critical current density of 10kA/cm2, a 2.4Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.
The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a Jc = 2.5 kA cm−2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a Jc = 10 kA cm−2, nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a Jc = 40 kA cm−2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.
We are investigating device yield in our Nb-nine-layer fabrication process for single-flux-quantum (SFQ) circuits, in which the critical current density of the Nb/AlOx/ Nb Josephson junction (JJ) is 10 kA/cm2and the minimum JJ size is 1 μm2. We fabricated several shift registers (SRs) with different sizes that exhibit bit capacities from 16 to 2560 bits on a chip on many wafers. The SR yields correlate roughly with process defect test results using diagnostic chips, which are included in all wafers and consist of various diagnostic patterns such as for interlayer and intralayer insulations. When the defect number was above a certain level, the SR yield drastically degraded. The other reason of SR yield degradation is poor size uniformity of JJ patterns. The JJ pattern resolutions using our i-line stepper depend on the several-μm-level flatness of wafers. All SRs on a chip consisting of 68 990 JJs operated correctly. We obtained both “good” and “poor” chips without intentional changes of process conditions. The “poor” chip was strongly affected by magnetic flux traps. We believe that determining the cause of this difference is key to fabricating SFQ circuits consisting of 100 000 or more JJs.
To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.
In NEC's standard process, the minimum junction size is 2 µm and the critical current density ( J C ) is 2.5 kA cm -2 . In the process, i-line stepper lithography and reactive ion etching with SF 6 gas are used and the standard deviation ( ) of the critical current ( I C ) was 0.9% for the 2 µm junctions. This junction uniformity enables integration of more than 10M junctions if an I C variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits.
We implemented, optimized, and fully tested a superconducting Josephson junction fabrication process over multiple runs tailored for integrated digital circuits that are used for control and readout of superconducting qubits operating at millikelvin temperatures. This process was optimized for highly energy efficient rapid single flux quantum (ERSFQ) circuits with critical currents reduced by a factor of ∼10 as compared to those operated at 4.2 K. Specifically, it implemented Josephson junctions with 10 μA unit critical current fabricated with 10 μA/μm2 critical current density. In order to circumvent the substantial size increase in the SFQ circuit inductors, we employed an NbN high kinetic inductance layer with 8.5 pH/sq sheet inductance. Similarly, to maintain the small size of junction resistive shunts, we used a non-superconducting PdAu alloy with 4.0 Ω/sq sheet resistance. For integration with quantum circuits in a multi-chip module, 5 and 10 μm height bump processes were also optimized. To keep the fabrication process in check, we developed and thoroughly tested a comprehensive process control monitor chip set.
Abstract We present SIMIT-Nb08, an eight-layer Nb-based fabrication process for double-active-layer single-flux-quantum (SFQ) digital circuits, aimed at overcoming the routing congestion and integration ‘density wall’ of planar SFQ designs. Both Nb/Al–AlO x /Nb JJ layers were designed with the same nominal critical current density of J c = 6 kA cm −2 , and the measured values were 6.15 and 6.26 kA cm −2 for the lower and upper JJ layers, respectively. This architecture incorporates a dual-ground-plane structure to reduce interlayer electromagnetic coupling and shield stray magnetic flux generated by bias lines. A stop-on-metal chemical mechanical polishing module was implemented to provide a controlled dielectric thickness and a planar surface for upper-layer device fabrication. We validate a double-layer SFQ logic cell library with wide DC bias margins on both layers, and demonstrate ultra-high-speed dynamic operation via a toggle flip-flop-based frequency-divider test exceeding 100 GHz. In addition, the process and cross-layer interconnect reliability are demonstrated by functional operation of a cross-layer one-bit full adder and an eight-bit shift register (SR), where the SR exhibits an effective junction-density improvement of ∼4× over typical single-layer implementations. Post-route benchmarking on a 320-cell SR indicates that SIMIT-Nb08 delivers substantial improvements in power, performance, and area, including a 32.2% reduction in area, a 25.0% increase in maximum operating frequency ( f max ), and a 65.3% reduction in estimated power compared with SIMIT-Nb03 (29.9%, 6.3%, and 62.5%, respectively, compared with SIMIT-Nb04), indicating its potential for routing-constrained SFQ digital circuits.