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Superconductor Science and Technology

Investigation of SFQ integrated circuits using Nb fabrication technology

Hideaki Numata, Masamitsu Tanaka, Y Kitagawa, Shuichi Tahara

Published Nov 1, 1999• 17 citations
Publisher

Abstract

In NEC's standard process, the minimum junction size is 2 µm and the critical current density ( J C ) is 2.5 kA cm -2 . In the process, i-line stepper lithography and reactive ion etching with SF 6 gas are used and the standard deviation ( ) of the critical current ( I C ) was 0.9% for the 2 µm junctions. This junction uniformity enables integration of more than 10M junctions if an I C variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits.

DOI
10.1088/0953-2048/12/11/361

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In NEC's standard process, the minimum junction size is 2 µm and the critical current density ( J C ) is 2.5 kA cm -2 . In the process, i-line stepper lithography and reactive ion etching with SF 6 gas are used and the standard deviation ( ) of the critical current ( I C ) was 0.9% for the 2 µm junctions. This junction uniformity enables integration of more than 10M junctions if an I C variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits.
We are investigating device yield in our Nb-nine-layer fabrication process for single-flux-quantum (SFQ) circuits, in which the critical current density of the Nb/AlOx/ Nb Josephson junction (JJ) is 10 kA/cm2and the minimum JJ size is 1 μm2. We fabricated several shift registers (SRs) with different sizes that exhibit bit capacities from 16 to 2560 bits on a chip on many wafers. The SR yields correlate roughly with process defect test results using diagnostic chips, which are included in all wafers and consist of various diagnostic patterns such as for interlayer and intralayer insulations. When the defect number was above a certain level, the SR yield drastically degraded. The other reason of SR yield degradation is poor size uniformity of JJ patterns. The JJ pattern resolutions using our i-line stepper depend on the several-μm-level flatness of wafers. All SRs on a chip consisting of 68 990 JJs operated correctly. We obtained both “good” and “poor” chips without intentional changes of process conditions. The “poor” chip was strongly affected by magnetic flux traps. We believe that determining the cause of this difference is key to fabricating SFQ circuits consisting of 100 000 or more JJs.
The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a Jc = 2.5 kA cm−2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a Jc = 10 kA cm−2, nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a Jc = 40 kA cm−2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.
We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 1×1μm, a line width of 0.8μm, a JJ critical current density of 10kA/cm2, a 2.4Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.
Submicron Nb/AlOx/Nb junctions having high critical current density of more than 20 kA/cm2are required for realizing single-flux-quantum (SFQ) circuits operating at a high speed of more than 100 GHz. We have developed a 20 kA/cm2process having submicron circular junctions. 1000-serially-connected circular shape junctions having six different diameters of 0.5 μm, 0.564 μm, 0.7 μm, 0.9 μm, 1.1 μm, and 1.3 μm have been designed. The 0.564 μm junction is designed to be 50 μA with critical current density of 20 kA/cm2, which is a minimum current value of a target SFQ circuit design. We totally fabricated 12 wafers with the 20 kA/cm2process. The 1σ spread of critical currents (Ic) depending on junction sizes and the run-to-run reproducibility of critical current densities are reported as a summary of these fabrications. We obtained Icscattering of 1σ≤ 2% even in the minimum circular junction of 0.25 μm2in several fabrication runs.
We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.
We report low-power single-flux-quantum (SFQ) circuits fabricated with a lowered critical current density process and low-voltage design. We selected 250 A/cm2^{2}2to obtain 2–10 μA Josephson junctions (JJs) easily using conventional facilities. Our numerical simulation shows that the expected operating frequency is 10 GHz and that we can reduce the bias voltage to 0.1–0.5 mV; power consumption can be reduced to around 1 nW per JJ. We newly developed a fabrication process featuring four planarized Nb layers and a Pd resistor layer. We obtained the correct operation of several basic SFQ circuit elements designed with the lowered critical currents to 1/2 of the conventional circuits at 4.2 K. We also evaluated the Josephson junction critical currents, specific capacitance, resistance, and inductance at 3 K and 300 mK. We observed an increase of 7% in the critical currents at 300 mK, while the other parameters were unchanged. We demonstrated a 0.5-mV Josephson transmission line where we lowered the critical currents to 1/10. We expect such low-power SFQ circuits to operate at 20 mK, providing classical, general-purpose digital processing near quantum bits.