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IEEE Transactions on Applied Superconductivity

Design and demonstration of fundamental logic circuits based on a single-flux-quantum gate with a resettable latch

Naoki Takeuchi, A. Akahori, N. Mori, Yasutoshi Suzuki, Futoshi Furuta, Akira Fujimaki, Hisao Hayakawa

Published Mar 1, 2001• 0 citations
Publisher

Abstract

We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.

DOI
10.1109/77.919509

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IEEE Transactions on Applied Superconductivity•Mar 1, 1993•10 citations
We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.
We report experimental demonstrations of logic functions based on single flux quantum logic with resettable latch (SFQ-RL) logic. SFQ-RL has been proposed as new SFQ logic, which enables us to initialize the whole circuit. This initialization function is essential for the state machine into which conventional SFQ logic is classified, and makes SFQ logic more applicable to a large-scale logic system, such as a processor. In addition, the function can prevent circuits from performing the failed operation caused by a trapped flux in storage loops. The logic consists of three primitives, which can compose any logic function. We have experimentally demonstrated the operation of "half adder" based on SFQ-RL with the bias margin of /spl plusmn/16%. In order to examine the function of initialization, we designed and evaluated a pseudo random sequence generator by numerical simulation. In addition, we experimentally confirmed the initialization of the generator and "circular buffer" with the bias margin of /spl plusmn/20%.
We propose new logic circuits based on Single Flux Quantum logic with Resettable Latch (SFQ-RL). This new logic enables us to initialize the whole circuit and realize an inverter easily. This initialization function is needed for general state machines, in addition, suppressing the failed operation caused by a trapped flux in storage loops. SFQ-RL logic consists of three primitives of gates, "Latch (L)-gate", "Copy(C)-gate" and "OR (O)-gate". L-gate is a kind of flip-flop gate. The difference from a conventional RSFQ latch, "RS-FF" is that L-gate can be reset without emitting an output pulse using "Initialize" pulse. Our numerical simulation shows that the bias margin of L-gate is /spl plusmn/8%. C-gate and O-gate correspond to "Splitter" and "Confluence Buffer" in RSFQ logic, respectively. Every logic function can be realized by only the three primitives. We confirmed the operations, "AND" and "OR" with reasonable margins and speeds by the numerical calculation. We have experimentally demonstrated the logic function such as OR based on SFQ-RL logic. We confirmed the normal operation of the gate with the bias margin of /spl plusmn/25.9%.
Rapid Single-Flux-Quantum Circuits Fabricated Using 20-kA/cm2\hbox{20}\hbox{-}\hbox{kA}/\hbox{cm}^{2}20-kA/cm2 Nb/AlOx/Nb\hbox{Nb}/\hbox{AlO}_{x}/\hbox{Nb}Nb/AlOx​/Nb Process
We designed and fabricated rapid single-flux-quantum (RSFQ) circuits using a new 20-kA/cm2process based on conventional Nb/AlOx/Nb Josephson junction (JJ) technology. Circular JJs were fabricated to improve their uniformity. They had sufficiently low spread of the critical currents for large-scale RSFQ circuits. We selected the circuit design parameters carefully, including the bias voltage and McCumber-Stewart parameter, balancing the energy consumption, switching speeds, margins, and integration density. We demonstrated several logic gates and shift registers at a clock frequency of 154 GHz with the designed bias voltage of 2.5 mV, and demonstrated energy-efficient shift registers using the low-voltage RSFQ (LV-RSFQ) technique at 83 GHz.
In NEC's standard process, the minimum junction size is 2 µm and the critical current density ( J C ) is 2.5 kA cm -2 . In the process, i-line stepper lithography and reactive ion etching with SF 6 gas are used and the standard deviation ( ) of the critical current ( I C ) was 0.9% for the 2 µm junctions. This junction uniformity enables integration of more than 10M junctions if an I C variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits.
We have proposed a cell-based design approach for rapid single flux quantum (RSFQ) logic circuits. In our design approach, a binary decision diagram (BDD) is used for representation of logical functions in order to reduce the number of gates. We have made a standard cell library, which is composed of only five basic cells. We add one-junction Josephson transmission line (JTL) to the edge of the input and the output node of some basic cells, by which no deterioration of the DC bias margin is observed for the connection of each cell. In the layout level, the size and the position of the input/output node of each cell are equalized. The standard cell circuits were fabricated by NEC 2.5 kA/cm/sup 2/ and Hypres 1.0 kA/cm/sup 2/ Nb standard process and they were tested at low speed.
The authors have optimized the design and calculated the margins for a number of single flux quantum (SFQ) logic elements, including AND, OR, XOR, splitter, DC-to-SFQ converter, and SFQ-to-DC converter. These are the fundamental building blocks necessary to construct more complex logic functions such as the half adder and full adder. Experimental tests of the primary gates, the AND, OR, XOR, and splitter, tests were made by imbedding each test gate between DC-to-SFQ converters at the inputs and SFQ-to-DC converters at the outputs. Automated testing of each circuit was used to determine functionality, optimum bias levels, and margins. The experimental bias current margins for each gate are consistent with the simulations.>