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IEEE Transactions on Applied Superconductivity

New logic circuits based on SFQ signals

Futoshi Furuta, Y. Suzuki, E Oya, S. Matsumoto, Hiroyuki Akaike, Akira Fujimaki, Hisao Hayakawa, Yoshiaki Takai

Published Jun 1, 1999• 8 citations
Publisher

Abstract

We propose new logic circuits based on Single Flux Quantum logic with Resettable Latch (SFQ-RL). This new logic enables us to initialize the whole circuit and realize an inverter easily. This initialization function is needed for general state machines, in addition, suppressing the failed operation caused by a trapped flux in storage loops. SFQ-RL logic consists of three primitives of gates, "Latch (L)-gate", "Copy(C)-gate" and "OR (O)-gate". L-gate is a kind of flip-flop gate. The difference from a conventional RSFQ latch, "RS-FF" is that L-gate can be reset without emitting an output pulse using "Initialize" pulse. Our numerical simulation shows that the bias margin of L-gate is /spl plusmn/8%. C-gate and O-gate correspond to "Splitter" and "Confluence Buffer" in RSFQ logic, respectively. Every logic function can be realized by only the three primitives. We confirmed the operations, "AND" and "OR" with reasonable margins and speeds by the numerical calculation. We have experimentally demonstrated the logic function such as OR based on SFQ-RL logic. We confirmed the normal operation of the gate with the bias margin of /spl plusmn/25.9%.

DOI
10.1109/77.783797

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We propose new logic circuits based on Single Flux Quantum logic with Resettable Latch (SFQ-RL). This new logic enables us to initialize the whole circuit and realize an inverter easily. This initialization function is needed for general state machines, in addition, suppressing the failed operation caused by a trapped flux in storage loops. SFQ-RL logic consists of three primitives of gates, "Latch (L)-gate", "Copy(C)-gate" and "OR (O)-gate". L-gate is a kind of flip-flop gate. The difference from a conventional RSFQ latch, "RS-FF" is that L-gate can be reset without emitting an output pulse using "Initialize" pulse. Our numerical simulation shows that the bias margin of L-gate is /spl plusmn/8%. C-gate and O-gate correspond to "Splitter" and "Confluence Buffer" in RSFQ logic, respectively. Every logic function can be realized by only the three primitives. We confirmed the operations, "AND" and "OR" with reasonable margins and speeds by the numerical calculation. We have experimentally demonstrated the logic function such as OR based on SFQ-RL logic. We confirmed the normal operation of the gate with the bias margin of /spl plusmn/25.9%.
We report experimental demonstrations of logic functions based on single flux quantum logic with resettable latch (SFQ-RL) logic. SFQ-RL has been proposed as new SFQ logic, which enables us to initialize the whole circuit. This initialization function is essential for the state machine into which conventional SFQ logic is classified, and makes SFQ logic more applicable to a large-scale logic system, such as a processor. In addition, the function can prevent circuits from performing the failed operation caused by a trapped flux in storage loops. The logic consists of three primitives, which can compose any logic function. We have experimentally demonstrated the operation of "half adder" based on SFQ-RL with the bias margin of /spl plusmn/16%. In order to examine the function of initialization, we designed and evaluated a pseudo random sequence generator by numerical simulation. In addition, we experimentally confirmed the initialization of the generator and "circular buffer" with the bias margin of /spl plusmn/20%.
We are introducing a new subfamily of rapid single-flux-quantum (RSFQ) digital cells, based on a single B flip-flop template. The template can be considered as an SFQ flip-flop with up to 4 inputs and 6 outputs. Each input SFQ pulse can change the flip-flop's internal state. Each output presents (in the form of SFQ pulses a specific logic function of the initial state of the cell and input signals. Simple connection of various inputs and/or outputs, combined with shortening or opening of certain branches of the template allows one to implement a variety of RSFQ cells with wide margins. Of these various RSFQ cells, we have designed and successfully tested the T1 cell (asynchronous toggle flip-flop with synchronous destructive readout), single-bit full adder, and single-bit stage of an up-down counter. Experimentally measured margins for dc power supply voltage for these circuits were /spl plusmn/24%, /spl plusmn/24%, and /spl plusmn/17%, respectively.>
We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.
We report on a voltage-state logic family based on shunted Josephson junctions and on the Rapid Single Flux Quantum (RSFQ) concept. Storing information in a voltage-state form makes this Multi-Flux-Quantum Logic (MFQL) easier to match to complementary metal-oxide semiconductor (CMOS) circuits. The switching of MFQL element between the voltage and zero-voltage states takes a minimum of two SFQ pulses, and the switching time of this logic is comparable to that of RSFQ logic. The key logic element is an inverter in the form of an asymmetric interferometer, and the underlying idea is to use a separate superconducting wire to supply a standard dc output voltage for the elements. The asymmetric interferometer, directly coupled to the other elements, is actually a Josephson junction based three-terminal device or transistor. Elements such as NOT, OR, NOR, XOR, XNOR, a toggle flip-flop, and an RS trigger have been simulated, and show margins better than /spl plusmn/24%. The performance of this logic with current circuit fabrication technologies is also discussed.
Novel reconfigurable superconductive single flux quantum (SFQ) logic devices, the functions of which can be dynamically reconfigured by inputting control signals, have been investigated. The characteristics of single flux quantum circuits can be easily modulated by applying currents or magnetic fields because of the high sensitivity of superconductive circuits. We investigated several design approaches for the realization of dynamically reconfigurable SFQ logic devices. We employed direct current injection to the logic gate using a non-destructive read-out flip-flop. By changing the internal state of the non-destructive read-out flip-flop, the logic function can be dynamically reconfigured. We have designed and tested a dynamically reconfigurable Josephson transmission line (JTL)/delay flip-flop (DFF) circuit. The measured dc bias margin was 72.5-107.2%. Furthermore, we have demonstrated the operation of a variable bit-length shift register, composed of the dynamically reconfigurable JTL/DFF circuits. The investigated design approach can be applied to more sophisticated dynamically reconfigurable single flux quantum logic gates.
This paper presents a basic circuit concept for pulse-driven asynchronous circuits using superconducting rapid single-flux-quantum (RSFQ) logic gates. Today's computer systems perform using a synchronous clock distributed over the whole system. The distribution of the clock signal becomes more difficult as the clock frequency increases because the wavelength of the clock signal becomes shorter than the system size. One way to solve this problem is to use asynchronous circuits in which all circuits perform their functions only under the law of cause and effect. We propose an implementation of the basic asynchronous circuit performing OR/AND logic operations between SFQ pulses. The operations are confirmed by SPICE simulation. We will show a design method for combinational circuits using the proposed basic circuits.