Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

Demonstration of 17 GHz operation of M-code generator based on SFQ with resettable latch

A. Akahori, Naoki Takeuchi, N. Mori, Y. Suzuki, Futoshi Furuta, Akira Fujimaki, Hisao Hayakawa

Published Mar 1, 2001• 6 citations
Publisher

Abstract

We have experimentally demonstrated high-speed operation of a maximum code length (M-code) generator using the on-chip-testing system. M-code generator was designed by using Single Flux Quantum with Resettable Latch (SFQ-RL) proposed by us, and fabricated by the NEC standard process. The circuit operates up to 17 GHz correctly, while the bias margin decreases at higher frequencies due to the timing-related errors. This circuit based on SFQ-RL has an advantage that the initialization of the whole circuit can be realized easily. We have also confirmed the "flush" operation that the internal state is initialized simultaneously by one SFQ pulse in SFQ-RL.

DOI
10.1109/77.919397

Related papers

Experimental demonstration of single flux quantum logic with resettable latch

Futoshi Furuta, A. Akahori, N. Mori +6 more

We report experimental demonstrations of logic functions based on single flux quantum logic with resettable latch (SFQ-RL) logic. SFQ-RL has been proposed as new SFQ logic, which enables us to initialize the whole circuit. This initialization function is essential for the state machine into which conventional SFQ logic is classified, and makes SFQ logic more applicable to a large-scale logic system, such as a processor. In addition, the function can prevent circuits from performing the failed operation caused by a trapped flux in storage loops. The logic consists of three primitives, which can compose any logic function. We have experimentally demonstrated the operation of "half adder" based on SFQ-RL with the bias margin of /spl plusmn/16%. In order to examine the function of initialization, we designed and evaluated a pseudo random sequence generator by numerical simulation. In addition, we experimentally confirmed the initialization of the generator and "circular buffer" with the bias margin of /spl plusmn/20%.

IEEE Transactions on Applied Superconductivity•Jun 1, 2000•5 citations

High-speed operation of RSFQ circuits up to 30 GHz

Futoshi Furuta, Yasutoshi Suzuki, H. Hasegawa +3 more

We have experimentally demonstrated high-speed operation of RSFQ circuits using on-chip testing system and confirmed normal operation up to 30 GHz. The system includes high-frequency pulse generators and shift registers (SRs) serving as an interface circuit between high-speed internal signals and low-speed external signals. We adopted two ladder-type pulse generators. One generates clock pulses of 10 GHz and the other generates 25 GHz. By increasing bias currents of JTLs, clock pulses can be generated at higher frequency. By using the system, an SR and a T flip-flop (TFF) gate are examined. The circuits were fabricated by NEC's standard process based on Nb/AlO x /Nb junction technology with J c = 2.5 kA cm -2 . We optimized circuit parameters by using Monte Carlo simulation. In addition, the effect of parasitic inductances can be reduced by decreasing I c . As a result, the systems for SR and TFF worked correctly up to 30 GHz and 27.5 GHz, respectively. The SR and TFF have wide bias margins of ±39% and ±20%, respectively. We confirmed that the bias margins of the SR are independent of operation frequency. The limits of operation frequency are thought to be much higher than 30 GHz.

Superconductor Science and Technology•Nov 1, 1999•8 citations

High-Speed Operation of a Single-Flux-Quantum (SFQ) Cross/Bar Switch up to 35 GHz

義男 亀田, Shinichi Yorozu, Hirotaka Terai +1 more

Single-flux-quantum (SFQ) technology is a novel technology where binary information is represented by a single flux. It enables us to realize high-speed, low-power SFQ logic circuits, surpassing conventional complementary metal-oxide-silicon (CMOS) technology. We proposed an SFQ packet switch to avoid the bottlenecks in broadband networks of the future. To demonstrate high-speed operation of an SFQ logic circuit and its application to our switch architecture, we designed a cross/bar switch. It consists of 13 logic gates and 581 Josephson junctions were used in the layout. We confirmed correct operations up to 33 GHz in simulation. We placed the switch circuit in an on-chip test system for high-speed (over 10 GHz) test. Including I/O circuits, the system as a whole consists of 1236 Josephson junctions. The chip was fabricated by using NEC's standard Nb process. We carried out an on-chip test and found correct operations up to 35 GHz.

Japanese Journal of Applied Physics•Apr 30, 2003•8 citations

Design and demonstration of fundamental logic circuits based on a single-flux-quantum gate with a resettable latch

Naoki Takeuchi, A. Akahori, N. Mori +4 more

We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.

IEEE Transactions on Applied Superconductivity•Mar 1, 2001•0 citations

High-Speed Demonstration of Single-Flux-Quantum Cross–Bar Switch up to 50 GHz

Y. Kameda, Shinichi Yorozu, Y. Hashimoto +3 more

We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.

IEEE Transactions on Applied Superconductivity•Mar 1, 2005•15 citations

Demonstration of a 120 GHz single-flux-quantum shift register circuit based on a 10 kA cm−2Nb process

Hiroyuki Akaike, Takahiro Yamada, Akira Fujimaki +5 more

Designs and test results for a single-flux-quantum (SFQ) eight-bit shift register circuit operating at frequencies above 100 GHz are described. The high-speed performance was realized by introducing a planarized 10 kA cm −2 Nb fabrication process as an advanced process and by adopting middle-damped junctions with McCumber parameters β c of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsion between SFQ pulses and to adjust the timing. The circuit was designed using a cell-based design method and was tested by constructing an on-chip test system with a ladder-type four-bit high-frequency clock generator. We confirmed its correct operations up to 120 GHz.

Superconductor Science and Technology•Mar 16, 2006•33 citations
We have experimentally demonstrated high-speed operation of a maximum code length (M-code) generator using the on-chip-testing system. M-code generator was designed by using Single Flux Quantum with Resettable Latch (SFQ-RL) proposed by us, and fabricated by the NEC standard process. The circuit operates up to 17 GHz correctly, while the bias margin decreases at higher frequencies due to the timing-related errors. This circuit based on SFQ-RL has an advantage that the initialization of the whole circuit can be realized easily. We have also confirmed the "flush" operation that the internal state is initialized simultaneously by one SFQ pulse in SFQ-RL.
We report experimental demonstrations of logic functions based on single flux quantum logic with resettable latch (SFQ-RL) logic. SFQ-RL has been proposed as new SFQ logic, which enables us to initialize the whole circuit. This initialization function is essential for the state machine into which conventional SFQ logic is classified, and makes SFQ logic more applicable to a large-scale logic system, such as a processor. In addition, the function can prevent circuits from performing the failed operation caused by a trapped flux in storage loops. The logic consists of three primitives, which can compose any logic function. We have experimentally demonstrated the operation of "half adder" based on SFQ-RL with the bias margin of /spl plusmn/16%. In order to examine the function of initialization, we designed and evaluated a pseudo random sequence generator by numerical simulation. In addition, we experimentally confirmed the initialization of the generator and "circular buffer" with the bias margin of /spl plusmn/20%.
We have experimentally demonstrated high-speed operation of RSFQ circuits using on-chip testing system and confirmed normal operation up to 30 GHz. The system includes high-frequency pulse generators and shift registers (SRs) serving as an interface circuit between high-speed internal signals and low-speed external signals. We adopted two ladder-type pulse generators. One generates clock pulses of 10 GHz and the other generates 25 GHz. By increasing bias currents of JTLs, clock pulses can be generated at higher frequency. By using the system, an SR and a T flip-flop (TFF) gate are examined. The circuits were fabricated by NEC's standard process based on Nb/AlO x /Nb junction technology with J c = 2.5 kA cm -2 . We optimized circuit parameters by using Monte Carlo simulation. In addition, the effect of parasitic inductances can be reduced by decreasing I c . As a result, the systems for SR and TFF worked correctly up to 30 GHz and 27.5 GHz, respectively. The SR and TFF have wide bias margins of ±39% and ±20%, respectively. We confirmed that the bias margins of the SR are independent of operation frequency. The limits of operation frequency are thought to be much higher than 30 GHz.
Single-flux-quantum (SFQ) technology is a novel technology where binary information is represented by a single flux. It enables us to realize high-speed, low-power SFQ logic circuits, surpassing conventional complementary metal-oxide-silicon (CMOS) technology. We proposed an SFQ packet switch to avoid the bottlenecks in broadband networks of the future. To demonstrate high-speed operation of an SFQ logic circuit and its application to our switch architecture, we designed a cross/bar switch. It consists of 13 logic gates and 581 Josephson junctions were used in the layout. We confirmed correct operations up to 33 GHz in simulation. We placed the switch circuit in an on-chip test system for high-speed (over 10 GHz) test. Including I/O circuits, the system as a whole consists of 1236 Josephson junctions. The chip was fabricated by using NEC's standard Nb process. We carried out an on-chip test and found correct operations up to 35 GHz.
We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.
Designs and test results for a single-flux-quantum (SFQ) eight-bit shift register circuit operating at frequencies above 100 GHz are described. The high-speed performance was realized by introducing a planarized 10 kA cm −2 Nb fabrication process as an advanced process and by adopting middle-damped junctions with McCumber parameters β c of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsion between SFQ pulses and to adjust the timing. The circuit was designed using a cell-based design method and was tested by constructing an on-chip test system with a ladder-type four-bit high-frequency clock generator. We confirmed its correct operations up to 120 GHz.