Future development of superconductor digital and mixed-signal ICs requires extensive testing with a large number of input/output (I/O) lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. There is a growing need for a standardized test apparatus for a variety of complex superconducting chips and multichip modules (MCMs). Such a test apparatus must support many I/O lines, be easy and cost-effective to operate, and support prolonged automated testing. Existing test apparatus include liquid He cryoprobes and cryocooled custom digital-RF systems, both of which have drawbacks. Liquid He cryoprobes with universal wiring, such as 40 or 80 coaxial cables, are convenient to use. Cooled by immersion in a tank filled with liquid He, these cryoprobes allow rapid cool-down and warm-up. However, large consumption of liquid He, the cost of which has been steadily increasing worldwide, makes this solution rather expensive and wasteful. On the other hand, one can exploit the modular reconfigurability of HYPRES' digital-RF receiver product to create a testbed for different ICs. Such a system uses the smallest commercially available closed-cycle refrigerator (~1.2 kW) and has negligible operating cost. However, reconfiguration takes time and expertise since these products are specially designed with customized chip package and wiring to minimize the thermal load on the cryocooler. These low-maintenance systems are ideal for prolonged operation of a single chip, which is invaluable for superconductor electronics system developers and end-users. The integrated cryoelectronics testbed (ICE-T) combines the advantages of the liquid He cryoprobe and the cryocooled digital-RF product. By using a more powerful, commercially available, electrically powered closed-cycle refrigerator (7 kW), ICE-T alleviates the thermal constraints on wiring while maintaining very low operating cost. By separating the electrical and thermal subsystems, it maintains modularity without sacrificing the universality of the cryoprobe. A set of universal and custom electrical modules can be independently built and inserted in ICE-T. Universal inserts with 40 and 80 coaxial cables accommodate all chips with standard I/O pads like the familiar liquid He cryoprobes. Custom inserts for different classes of chips and MCMs are designed and built according to user requirements and specifications. The utility of the ICE-T was successfully demonstrated by testing a benchmark superconducting digital circuit at low frequency and an analog-to-digital converter chip clocked above 20 GHz.
Future development of superconductor digital and mixed-signal ICs requires extensive testing with a large number of input/output (I/O) lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. There is a growing need for a standardized test apparatus for a variety of complex superconducting chips and multichip modules (MCMs). Such a test apparatus must support many I/O lines, be easy and cost-effective to operate, and support prolonged automated testing. Existing test apparatus include liquid He cryoprobes and cryocooled custom digital-RF systems, both of which have drawbacks. Liquid He cryoprobes with universal wiring, such as 40 or 80 coaxial cables, are convenient to use. Cooled by immersion in a tank filled with liquid He, these cryoprobes allow rapid cool-down and warm-up. However, large consumption of liquid He, the cost of which has been steadily increasing worldwide, makes this solution rather expensive and wasteful. On the other hand, one can exploit the modular reconfigurability of HYPRES' digital-RF receiver product to create a testbed for different ICs. Such a system uses the smallest commercially available closed-cycle refrigerator (~1.2 kW) and has negligible operating cost. However, reconfiguration takes time and expertise since these products are specially designed with customized chip package and wiring to minimize the thermal load on the cryocooler. These low-maintenance systems are ideal for prolonged operation of a single chip, which is invaluable for superconductor electronics system developers and end-users. The integrated cryoelectronics testbed (ICE-T) combines the advantages of the liquid He cryoprobe and the cryocooled digital-RF product. By using a more powerful, commercially available, electrically powered closed-cycle refrigerator (7 kW), ICE-T alleviates the thermal constraints on wiring while maintaining very low operating cost. By separating the electrical and thermal subsystems, it maintains modularity without sacrificing the universality of the cryoprobe. A set of universal and custom electrical modules can be independently built and inserted in ICE-T. Universal inserts with 40 and 80 coaxial cables accommodate all chips with standard I/O pads like the familiar liquid He cryoprobes. Custom inserts for different classes of chips and MCMs are designed and built according to user requirements and specifications. The utility of the ICE-T was successfully demonstrated by testing a benchmark superconducting digital circuit at low frequency and an analog-to-digital converter chip clocked above 20 GHz.
Superconductor microelectronics (SME) are rapidly redefining the state-of-the-art in wireless RF performance. SME-based digital RF subsystems, enabled by compact cryocoolers, have the potential to achieve all JTRS objective requirements (not just the thresholds) for performance, SWaP, and Cost as an Independent Variable (CAIV) targets for clusters 1, 3 and 4. Compact cryo-packaging is the key to deploying SME-based digital RF subsystems in JTRS and other wireless radio systems. A compact cryocooler provides the cryogenic environment for the superconductor multi-chip modules (MCM). The cryo-package (comprising the MCM and compact cryocooler) includes the mechanical and electrical interfaces to the JTRS radio. For example, a single SME-based digital RF subsystem provides a 10-channel full-duplex transceiver in less than 500 in/sup 3/, 30 lbs, and 150 watts; and an availability (up time) on the order of 99.998%. This paper discusses all aspects of cryopackaging, which include compact closed-cycle refrigerators or cryocoolers, methods of building and cooling superconductor multi-chip modules, managing thermal loads of input-output leads between warm ambient temperature electronics and cold superconductor electronics, and electromagnetic shielding.
We demonstrate a packaging system/test probe suitable for testing complex, large scale superconducting integrated circuits with thousands of Josephson junctions. The cryopackage is designed to work with a 1 cm superconducting die, with liquid He immersion cooling using a standard storage dewar. The package has 80 high-speed input-output lines (DC to 20 GHz) which connect the chip to room temperature electronics. The tip of the cryopackage, containing the chip, is shielded from the ambient magnetic field with two mumetal cylinders and contains a built-in coil, which provides in-situ degaussing of the inner shield. To clear flux trapped in the chip being tested, the probe contains a novel gas manifold and a system of heaters. During the defluxing operation, a heater evaporates liquid helium inside the chip enclosure, the expanding vapor purging the liquid from the sample cell and warming the chip above its transition temperature. Once the chip is defluxed, the liquid helium is allowed back into the cell, at a rate slow enough to avoid trapping flux in the chip while it is cooled. The process can be automated and does not require any movement of the probe once inserted in the dewar.
Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ∼30GHz clock frequencies.
NbN RSFQ circuits operating at 9 K reduce the cooling constraints especially for portable, remote, telecoms or medical imaging applications. We have developed a test-bed to study the operating temperature of the various mixed RF and digital circuit blocks of NbN ‘HyperSCAN’ project test vehicle 1cm2chips. The use of a widespread helium cryostat (‘Orange-ILL’) allows us to stabilize the chip temperature in the range 2.9 K–20 K with thermal oscillations lower than 0.1 K. The chip is mounted on a PCB and shielded from the external field: the PCB provides a multi-connection packaging used in order to study temperature and frequency operation of 30 GHz NbTiN CPW filters, RSFQ gates, analog SQUID and NbN/TaN/NbN SNS junctions arrays. The comparison between electrical simulations and tests is made on flexible,$\sim56cmlong,micro−striplineribboncablecarrying32signalseachincludingbiaslines,intherangeofDC−3GHz,combinedwith4semi−rigid\sim$40 GHz coaxial cables. By removing spurious resonances, it is expected to take full benefit of the large bandwidth, low insertion loss and low thermal conductivity of the set-up. We emphasis on the flexibility, large yield, reliability and reduced cost of such packaging coupled to He cooling exchanger for applying to testers and to future 9 K NbN multi-ADC green and remote systems when only low electrical power sources are available.
HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of RF lines and resistance of DC bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g., ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of high-speed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.
Improving the efficiency in digital data transport, originating from 4 K superconductor integrated circuits (ICs) to standard room-temperature (300 K) electronics, both in terms of speed and power consumption, is vitally important for nearly all applications of superconductor digital electronics. The required data link must include all necessary amplification and conditioning to convert digital data from single flux quantum (SFQ) logic to standard CMOS logic levels. Therefore, one must minimize the overall power consumption for the required total data throughout by taking into account all parts of the link: (1) data transmitters or output drivers with SFQ input, (2) additional amplifiers, (3) transmission lines, and (4) data receivers at room-temperature, such as the ones available on commercial field-programmable gate arrays (FPGAs). Here, we describe two variants of electrical data links, with and without cryogenic semiconductor amplifiers.