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IEEE Sarnoff Symposium

Highly compact and efficient JTRS radios using superconductor microelectronics - a quantum leap in performance: the cryopackage

Elie K. Track, Richard Hitt, Deepnarayan Gupta

Published Jun 3, 2004• 2 citations
Publisher

Abstract

Superconductor microelectronics (SME) are rapidly redefining the state-of-the-art in wireless RF performance. SME-based digital RF subsystems, enabled by compact cryocoolers, have the potential to achieve all JTRS objective requirements (not just the thresholds) for performance, SWaP, and Cost as an Independent Variable (CAIV) targets for clusters 1, 3 and 4. Compact cryo-packaging is the key to deploying SME-based digital RF subsystems in JTRS and other wireless radio systems. A compact cryocooler provides the cryogenic environment for the superconductor multi-chip modules (MCM). The cryo-package (comprising the MCM and compact cryocooler) includes the mechanical and electrical interfaces to the JTRS radio. For example, a single SME-based digital RF subsystem provides a 10-channel full-duplex transceiver in less than 500 in/sup 3/, 30 lbs, and 150 watts; and an availability (up time) on the order of 99.998%. This paper discusses all aspects of cryopackaging, which include compact closed-cycle refrigerators or cryocoolers, methods of building and cooling superconductor multi-chip modules, managing thermal loads of input-output leads between warm ambient temperature electronics and cold superconductor electronics, and electromagnetic shielding.

DOI
10.1109/sarnof.2004.1302847

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Superconductor microelectronics (SME) are rapidly redefining the state-of-the-art in wireless RF performance. SME-based digital RF subsystems, enabled by compact cryocoolers, have the potential to achieve all JTRS objective requirements (not just the thresholds) for performance, SWaP, and Cost as an Independent Variable (CAIV) targets for clusters 1, 3 and 4. Compact cryo-packaging is the key to deploying SME-based digital RF subsystems in JTRS and other wireless radio systems. A compact cryocooler provides the cryogenic environment for the superconductor multi-chip modules (MCM). The cryo-package (comprising the MCM and compact cryocooler) includes the mechanical and electrical interfaces to the JTRS radio. For example, a single SME-based digital RF subsystem provides a 10-channel full-duplex transceiver in less than 500 in/sup 3/, 30 lbs, and 150 watts; and an availability (up time) on the order of 99.998%. This paper discusses all aspects of cryopackaging, which include compact closed-cycle refrigerators or cryocoolers, methods of building and cooling superconductor multi-chip modules, managing thermal loads of input-output leads between warm ambient temperature electronics and cold superconductor electronics, and electromagnetic shielding.
Superconductor microelectronics (SME) enables the realization of the true digital-RF architecture, extending the flexibility and fidelity of digital processing up to multi-GRz speeds. HYPRES is developing digital-RF subsystems that provide wideband and narrowband OBJECTIVE-level performance for WIN-T, FCS, TCA and JTRS communications systems. These subsystems are designed for near-term insertion into existing and future systems providing dramatic performance improvements and major reductions in SWaP and life cycle cost. This quantum electronics technology provides a quantum leap in performance ypassing the slow incremental improvements of traditional mostly analog electronics - to revolutionize future RF systems. This revolutionary SME technology provides unparalleled accuracies, spectral purities and ultra fast speeds that are otherwise unattainable with competing semiconductor technologies. The advantages and features of SME technology can be applied to a wide range of military satellite communications applications to include an extended family of JTRS SCA compliant radios in the 2 GHz to 55 GHz band and digital beamforming (DBF) phased arrays that make SATCOM-On-The-Move (SOTM) viable.
Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ∼30GHz clock frequencies.
Future development of superconductor digital and mixed-signal ICs requires extensive testing with a large number of input/output (I/O) lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. There is a growing need for a standardized test apparatus for a variety of complex superconducting chips and multichip modules (MCMs). Such a test apparatus must support many I/O lines, be easy and cost-effective to operate, and support prolonged automated testing. Existing test apparatus include liquid He cryoprobes and cryocooled custom digital-RF systems, both of which have drawbacks. Liquid He cryoprobes with universal wiring, such as 40 or 80 coaxial cables, are convenient to use. Cooled by immersion in a tank filled with liquid He, these cryoprobes allow rapid cool-down and warm-up. However, large consumption of liquid He, the cost of which has been steadily increasing worldwide, makes this solution rather expensive and wasteful. On the other hand, one can exploit the modular reconfigurability of HYPRES' digital-RF receiver product to create a testbed for different ICs. Such a system uses the smallest commercially available closed-cycle refrigerator (~1.2 kW) and has negligible operating cost. However, reconfiguration takes time and expertise since these products are specially designed with customized chip package and wiring to minimize the thermal load on the cryocooler. These low-maintenance systems are ideal for prolonged operation of a single chip, which is invaluable for superconductor electronics system developers and end-users. The integrated cryoelectronics testbed (ICE-T) combines the advantages of the liquid He cryoprobe and the cryocooled digital-RF product. By using a more powerful, commercially available, electrically powered closed-cycle refrigerator (7 kW), ICE-T alleviates the thermal constraints on wiring while maintaining very low operating cost. By separating the electrical and thermal subsystems, it maintains modularity without sacrificing the universality of the cryoprobe. A set of universal and custom electrical modules can be independently built and inserted in ICE-T. Universal inserts with 40 and 80 coaxial cables accommodate all chips with standard I/O pads like the familiar liquid He cryoprobes. Custom inserts for different classes of chips and MCMs are designed and built according to user requirements and specifications. The utility of the ICE-T was successfully demonstrated by testing a benchmark superconducting digital circuit at low frequency and an analog-to-digital converter chip clocked above 20 GHz.
Packaging of a superconducting electronic system on a compact multistage cryocooler requires careful management of thermal loads from input and output leads, in order not to exceed the heat lift capacity of the various stages of the cooler. In particular, RSFQ systems typically require a large total bias current or greater. A general analysis of resistive wires shows that the tradeoff between heat flow and Joule heating yields a minimum heat load from optimized bias leads on a low- stage, given by , where is the thermalization temperature of the leads on the previous (hotter) stage. This is independent of the material, number, and geometry of the leads, as long as the total lead resistance is optimized. A similar tradeoff between heat flow and signal attenuation can be applied to the optimization of high-frequency input/output lines. Superconducting leads are not subject to these limitations, and can result in further reduction in heat load. Design examples are presented for an RSFQ-based radio receiver on either a two-stage or a four-stage cooler.
We have demonstrated the full operation of digital RF receivers on a HYPRES-designed cryostat, which couples an Nb-based superconducting Rapid Single Flux Quantum (RSFQ) chip to a commercially available 100 mW 4 Kelvin Gifford-McMahon cryocooler. A field demonstration of digitization of a satellite-received signal at 7.7 GHz is described. The digital receiver chip is a 1 cm×1 cm chip comprising ∼11,000 Josephson junctions (JJ). The measured cryogenic thermal and magnetic environments of the chip are discussed and their impact on performance. Reception and direct digital conversion of real signals in the HF-, VHF-, and X-bands including signals from military satellite antennae shows the potential of this system to replace large and power-hungry multiple analog receivers.
HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of RF lines and resistance of DC bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g., ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of high-speed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.