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IEEE Transactions on Applied Superconductivity

Current Leads and Optimized Thermal Packaging for Superconducting Systems on Multistage Cryocoolers

Alan M. Kadin, R.J. Webber, Deepnarayan Gupta

Published Jun 1, 2007• 29 citations
Publisher

Abstract

Packaging of a superconducting electronic system on a compact multistage cryocooler requires careful management of thermal loads from input and output leads, in order not to exceed the heat lift capacity of the various stages of the cooler. In particular, RSFQ systems typically require a large total bias current or greater. A general analysis of resistive wires shows that the tradeoff between heat flow and Joule heating yields a minimum heat load from optimized bias leads on a low- stage, given by , where is the thermalization temperature of the leads on the previous (hotter) stage. This is independent of the material, number, and geometry of the leads, as long as the total lead resistance is optimized. A similar tradeoff between heat flow and signal attenuation can be applied to the optimization of high-frequency input/output lines. Superconducting leads are not subject to these limitations, and can result in further reduction in heat load. Design examples are presented for an RSFQ-based radio receiver on either a two-stage or a four-stage cooler.

DOI
10.1109/tasc.2007.898719

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Packaging of a superconducting electronic system on a compact multistage cryocooler requires careful management of thermal loads from input and output leads, in order not to exceed the heat lift capacity of the various stages of the cooler. In particular, RSFQ systems typically require a large total bias current or greater. A general analysis of resistive wires shows that the tradeoff between heat flow and Joule heating yields a minimum heat load from optimized bias leads on a low- stage, given by , where is the thermalization temperature of the leads on the previous (hotter) stage. This is independent of the material, number, and geometry of the leads, as long as the total lead resistance is optimized. A similar tradeoff between heat flow and signal attenuation can be applied to the optimization of high-frequency input/output lines. Superconducting leads are not subject to these limitations, and can result in further reduction in heat load. Design examples are presented for an RSFQ-based radio receiver on either a two-stage or a four-stage cooler.
Low‐temperature electronic systems require electrical leads which have low electrical resistance to provide bias current Ibias without excessive voltage drop Vlead. But proper cryogenic design also requires high thermal resistance to maintain a minimal heat leak Q̇ from the hot temperature Thot to the cold temperature Tcold. By the Wiedemann‐Franz law, these requirements are in direct conflict, and the optimal configuration takes a particularly simple universal approximate form for the common case that Tcold << Thot: Q̇min/Ibias ≈ Vlead ≈ 3.6 kBThot/e. This is applied here to the cryopackaging of RSFQ superconducting circuits on a 4 K cryocooler, but is equally applicable to other cryogenic systems such as superconducting sensor arrays at low and ultra‐low temperatures.
Superconductor microelectronics (SME) are rapidly redefining the state-of-the-art in wireless RF performance. SME-based digital RF subsystems, enabled by compact cryocoolers, have the potential to achieve all JTRS objective requirements (not just the thresholds) for performance, SWaP, and Cost as an Independent Variable (CAIV) targets for clusters 1, 3 and 4. Compact cryo-packaging is the key to deploying SME-based digital RF subsystems in JTRS and other wireless radio systems. A compact cryocooler provides the cryogenic environment for the superconductor multi-chip modules (MCM). The cryo-package (comprising the MCM and compact cryocooler) includes the mechanical and electrical interfaces to the JTRS radio. For example, a single SME-based digital RF subsystem provides a 10-channel full-duplex transceiver in less than 500 in/sup 3/, 30 lbs, and 150 watts; and an availability (up time) on the order of 99.998%. This paper discusses all aspects of cryopackaging, which include compact closed-cycle refrigerators or cryocoolers, methods of building and cooling superconductor multi-chip modules, managing thermal loads of input-output leads between warm ambient temperature electronics and cold superconductor electronics, and electromagnetic shielding.
A robust cryogenic infrastructure in form of a wired, thermally optimized dilution refrigerator is essential for solid-state based quantum processors. Here, we engineer a cryogenic setup, which minimizes passive and active heat loads, while guaranteeing rapid qubit control and readout. We review design criteria for qubit drive lines, flux lines, and output lines used in typical experiments with superconducting circuits and describe each type of line in detail. The passive heat load of stainless steel and NbTi coaxial cables and the active load due to signal dissipation are measured, validating our robust and extensible concept for thermal anchoring of attenuators, cables, and other microwave components. Our results are important for managing the heat budget of future large-scale quantum computers based on superconducting circuits.
Niobium based rapid-single-flux-quantum (RSFQ) digital circuits generally operate at temperature 4 K. It is desirable to develop RSFQ circuits for operation at much lower temperatures, in particular to use as control and interface circuitry for superconducting qubits, and eventually for a full scale quantum computer. The total heat load is moderate - current designs generate 0.5 /spl mu/W per bias resistor, so simple RSFQ integrated circuits are easily compatible with commercial helium dilution refrigerators, and this power can readily be reduced by several orders of magnitude for complex future designs - but thermal conductivity will be a bottleneck. We present a simple model of heat flow through standard RSFQ structures. We find that circuits designed for 4 K operation can be used with little or no modification below one Kelvin. At lower temperatures however the heat generated on chip cannot be removed, and the temperature of a working circuit will rise. We suggest fabrication design rule changes to address this problem.
The readout amplification chain imposes a critical thermal scalability bottleneck in large-scale superconducting quantum systems. This happens through three mechanisms: amplifier dissipation, passive conduction through bias wiring and Joule heating within that same wiring. These terms are absent or only partially represented in several prior system-level thermal-scalability models, leading to bottleneck misidentification and scalability overestimation. In this work, we improve upon previous system-level heat estimation models by fully accounting for the major heat sources in modern cryogenic quantum systems including the active dissipation, passive conduction, and Joule heating in the readout amplifier module. Our analysis demonstrates that amplifier-associated heat emerges as the dominant thermal bottleneck that fundamentally alters the thermal landscape of modern large-scale cryogenic systems. We explore various technology options and their tradeoffs to identify configurations that reduce this critical heat load and improve scalability. Finally, we evaluate forward-looking system configurations, including larger refrigeration platforms and optical approaches, and analyze forward-looking pathways toward single-fridge 10k-qubit cryogenic systems.
HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of RF lines and resistance of DC bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g., ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of high-speed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.