Revisiting Thermal Scalability for Large-Scale Superconducting Quantum Systems

Abstract

The readout amplification chain imposes a critical thermal scalability bottleneck in large-scale superconducting quantum systems. This happens through three mechanisms: amplifier dissipation, passive conduction through bias wiring and Joule heating within that same wiring. These terms are absent or only partially represented in several prior system-level thermal-scalability models, leading to bottleneck misidentification and scalability overestimation. In this work, we improve upon previous system-level heat estimation models by fully accounting for the major heat sources in modern cryogenic quantum systems including the active dissipation, passive conduction, and Joule heating in the readout amplifier module. Our analysis demonstrates that amplifier-associated heat emerges as the dominant thermal bottleneck that fundamentally alters the thermal landscape of modern large-scale cryogenic systems. We explore various technology options and their tradeoffs to identify configurations that reduce this critical heat load and improve scalability. Finally, we evaluate forward-looking system configurations, including larger refrigeration platforms and optical approaches, and analyze forward-looking pathways toward single-fridge 10k-qubit cryogenic systems.

The paper asks how readout-amplifier dissipation and bias wiring affect thermal limits in superconducting quantum computers as improved interconnects and refrigeration reduce millikelvin-stage loads. It extends system-level heat accounting to include passive conduction, active dissipation, and Joule heating across refrigerator stages, comparing amplifier technologies, wiring materials, and cooling profiles. Dynamic loads are averaged over surface-code syndrome-extraction circuits for an eight-qubit unit cell, then scaled linearly. Reconstructed configurations show bottleneck migration toward 4 K when lower-conduction wiring and stronger refrigeration are introduced. Including amplifier-bias conduction reduces one high-density-wiring configuration’s estimated capacity from a previously reported approximately 144 qubits to approximately 80. Under the assumed geometry, three AWG30 copper bias wires contribute approximately 20 mW per amplifier at 4 K, exceeding a conventional HEMT’s 7.8 mW active dissipation. For a modeled KIDE configuration, replacing conventional HEMTs with copper biasing by low-power amplifiers with Manganin biasing increases capacity from 776 to 4,688 physical qubits; the mixing chamber then becomes limiting. Further wiring and cooling changes are evaluated as conditional pathways toward 10,000-qubit systems. Logical-memory capacity is estimated using Stim simulations and PyMatching decoding to select surface-code distances, excluding computational-layout overhead. The thermal framework assumes fixed stage temperatures below prescribed cooling limits and uniform linear scaling; some refrigerator capacities are estimated or projected. Amplifier-dependent readout noise is not modeled directly, and proposed SIS/YBCO configurations and optical pathways rely on emerging technologies or hypothetical operating assumptions rather than validated integrated systems.