Cryogenic capacity is a key bottleneck in the scaling of superconducting quantum processors, critically impacted by control wiring. Currently, wiring architectures are often designed following a small set of "best-practice" heuristics, little changed since they emerged for early, small-scale systems, and not rigorously evaluated for wider contexts. Here, we adopt a whole-system numerical modelling approach and present a systematic optimisation for the coaxial wiring design of a superconducting quantum processor. We identify optimised configurations that substantively outperform conventional designs in device temperature, noise burden, qubit capacity and other practical metrics. Importantly, our analysis delivers varied outcomes for different system contexts and operating regimes, illustrating the benefits of a systematic approach when there is no universal solution. Our results evaluate and sometimes challenge conventional wisdom in relation to design factors such as the utility of 0dB attenuators. We also use a wide exploration of cable configurations---directly enabled by our holistic and flexible numerical modelling approach---to develop more rigorously supported general principles for future cryogenic system design, based on a new conceptual framework to describe attenuator cascades that draws on analogies to low-noise amplifier chains. Our approach, design outcomes, and generalised analyses should also be readily applicable to other cryogenic quantum computing platforms. Finally, we support ready adoption of this approach through a web-based graphical tool which streamlines the analysis of the proposed framework under different contexts. Our results illustrate how our approach can help maximise the available computational resources of quantum processors at all system scales.
Cryogenic capacity is a key bottleneck in the scaling of superconducting quantum processors, critically impacted by control wiring. Currently, wiring architectures are often designed following a small set of "best-practice" heuristics, little changed since they emerged for early, small-scale systems, and not rigorously evaluated for wider contexts. Here, we adopt a whole-system numerical modelling approach and present a systematic optimisation for the coaxial wiring design of a superconducting quantum processor. We identify optimised configurations that substantively outperform conventional designs in device temperature, noise burden, qubit capacity and other practical metrics. Importantly, our analysis delivers varied outcomes for different system contexts and operating regimes, illustrating the benefits of a systematic approach when there is no universal solution. Our results evaluate and sometimes challenge conventional wisdom in relation to design factors such as the utility of 0dB attenuators. We also use a wide exploration of cable configurations---directly enabled by our holistic and flexible numerical modelling approach---to develop more rigorously supported general principles for future cryogenic system design, based on a new conceptual framework to describe attenuator cascades that draws on analogies to low-noise amplifier chains. Our approach, design outcomes, and generalised analyses should also be readily applicable to other cryogenic quantum computing platforms. Finally, we support ready adoption of this approach through a web-based graphical tool which streamlines the analysis of the proposed framework under different contexts. Our results illustrate how our approach can help maximise the available computational resources of quantum processors at all system scales.
Scaling superconducting quantum processors to hundreds of qubits is essential for demonstrating quantum advantage and implementing quantum error correction codes with larger distances. A key challenge is integrating control and readout wiring without compromising cryogenic or electronic performance. To address this, we performed a systematic analysis of the thermal budget within a dilution refrigerator and developed high-density 0.5 mm SCuNi-CuNi coaxial cable sets optimized for heat load management. This enables the integration of 696 control lines and 40 readout amplification chains into a dilution refrigerator with a cooling power of 1 mW at 100 mK, maintaining a stable base temperature of ∼8 mK for over a year. We validated the platform's performance with two large-scale quantum processors: a 540-qubit processor with an average T1 of 35 μs and a 156-qubit processor with 182 tunable couplers, achieving average fidelities of 99.9% for single-qubit gates and 99.0% for two-qubit gates. This study demonstrates a viable high-density wiring solution for controlling and measuring processors at the 500-qubit scale and provides critical engineering insights for larger-scale quantum computing systems.
A robust cryogenic infrastructure in form of a wired, thermally optimized dilution refrigerator is essential for solid-state based quantum processors. Here, we engineer a cryogenic setup, which minimizes passive and active heat loads, while guaranteeing rapid qubit control and readout. We review design criteria for qubit drive lines, flux lines, and output lines used in typical experiments with superconducting circuits and describe each type of line in detail. The passive heat load of stainless steel and NbTi coaxial cables and the active load due to signal dissipation are measured, validating our robust and extensible concept for thermal anchoring of attenuators, cables, and other microwave components. Our results are important for managing the heat budget of future large-scale quantum computers based on superconducting circuits.
As quantum computing technology advances, the demand for efficient, scalable, and thermally optimized solutions for qubit control and readout under cryogenic conditions has become increasingly critical. Currently, cryogenic qubit systems rely on numerous coaxial cables and DC wires for readout and control—typically two to three per qubit. Such dense wiring introduces significant engineering challenges, particularly regarding heat dissipation and spatial limitations [1]. To address these issues, wireless approaches have been proposed, offering promising advantages in scalability, thermal load reduction, and efficient quantum state transfer. Although wireless systems eliminate the need for cables, dilution refrigerators (DRs) impose strict spatial constraints, limiting the use of conventional microwave-range wireless components such as horn antennas and dielectric lenses. In addition, the sensitive and enclosed cryogenic environment demands precise beam shaping to prevent unwanted scattering and reflections. Hence, there is a pressing need for a compact and effective wireless solution tailored to such environments. In this study, we present a next-generation wireless communication system specifically designed for cryogenic quantum environments, enabling qubit control and readout at millikelvin temperatures. To achieve optimal signal transmission, we explored and simulated multiple design strategies, addressing challenges such as signal degradation, noise interference, and limited spatial volume within the refrigerator. Our system employs metasurface lens antennas to enhance transmission efficiency while minimizing signal-to-noise ratio (SNR) degradation. Considering the confined geometry of cryogenic setups, we developed two types of compact metalens antennas operating in both the microwave and millimeterwave regimes. Experimental measurements demonstrate more than 20 dB enhancement in wireless transmission, consistent with simulation results. These findings confirm that the proposed system satisfies the stringent requirements of quantum control and readout, making it a promising and practical solution for future quantum computing applications. We will share further details and insights on the metasurface-enabled wireless quantum computing platform at the upcoming conference presentation.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
Superconducting qubits are pivotal in advancing quantum computing, poised for scale but limited by the complexity and fidelity of their control and readout systems, relying on RF and signal processing infrastructure. This survey serves as a comprehensive and technically grounded review of control and readout architectures tailored for superconducting qubits. Synthesizing insights from device physics, circuit design, microwave engineering, signal processing, and cryogenic integration, this work details the practicalities of RF pulse generation, signal synthesis, and readout signal analysis for quantum systems. it covers key requirements, parameters, and pulse engineering techniques, including commonly used envelopes like Gaussian and DRAG designs. Moving to the system level, this survey systematically classifies and critically analyses current architectural strategies (covering key areas like frequency conversion, waveform management, and system infrastructure) and technology platforms (including adaptive classical control stacks, cryogenic CMOS circuits, and novel interconnects and interfaces), evaluating their trade-offs in performance. Extensive literature analysis identifies prevailing limitations such as wiring complexity, thermal budget constraints, latency, and power consumption, while highlighting underexplored opportunities for on-chip signal processing and novel interconnects, drawing analogies to advanced communication systems design. By consolidating diverse control paradigms and critically evaluating their trade-offs, this survey provides a unified foundation for designing next-generation quantum control stacks. Finally, a forward-looking roadmap outlines key trends in monolithic integration, cryo-compatible digital architectures, and physics-informed hardware co-design, offering both a retrospective synthesis and a prospective vision for quantum hardware engineering beyond the NISQ era.
Today's hundred-qubit quantum computers require a dramatic scale up to millions of qubits to become practical for solving real-world problems. Although a variety of qubit technologies have been demonstrated, scalability remains a major hurdle. Superconducting (SC) qubits are one of the most mature and promising technologies to overcome this challenge. However, these qubits reside in a millikelvin cryogenic dilution fridge, isolating them from thermal and electrical noise. They are controlled by a rack-full of external electronics through extremely complex wiring and cables. Although thousands of qubits can be fabricated on a single chip and cooled down to millikelvin temperatures, scaling up the control and readout electronics remains an elusive goal. This is mainly due to the limited available cooling power in cryogenic systems constraining the wiring capacity and cabling heat load management. In this article, we focus on scaling up the number of XY-control lines by using cryogenic RF-photonic links. This is one of the major roadblocks to build a thousand qubit superconducting QC. We will first review and study the challenges of state-of-the-art proposed approaches, including cryogenic CMOS and deep-cryogenic photonic methods, to scale up the control interface for SC qubit systems. We will discuss their limitations due to the active power dissipation and passive heat leakage in detail. By analytically modeling the noise sources and thermal budget limits, we will show that our solution can achieve a scale up to a thousand of qubits. Our proposed method can be seamlessly implemented using advanced silicon photonic processes, and the number of required optical fibers can be further reduced by using wavelength division multiplexing (WDM).