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IEEE Transactions on Applied Superconductivity

Thermal design of superconducting digital circuits for millikelvin operation

Thomas Ohki, Jonathan L. Habif, M. J. Feldman, Mark F. Bocko

Published Jun 1, 2003• 8 citations
Publisher

Abstract

Niobium based rapid-single-flux-quantum (RSFQ) digital circuits generally operate at temperature 4 K. It is desirable to develop RSFQ circuits for operation at much lower temperatures, in particular to use as control and interface circuitry for superconducting qubits, and eventually for a full scale quantum computer. The total heat load is moderate - current designs generate 0.5 /spl mu/W per bias resistor, so simple RSFQ integrated circuits are easily compatible with commercial helium dilution refrigerators, and this power can readily be reduced by several orders of magnitude for complex future designs - but thermal conductivity will be a bottleneck. We present a simple model of heat flow through standard RSFQ structures. We find that circuits designed for 4 K operation can be used with little or no modification below one Kelvin. At lower temperatures however the heat generated on chip cannot be removed, and the temperature of a working circuit will rise. We suggest fabrication design rule changes to address this problem.

DOI
10.1109/tasc.2003.814118

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Niobium based rapid-single-flux-quantum (RSFQ) digital circuits generally operate at temperature 4 K. It is desirable to develop RSFQ circuits for operation at much lower temperatures, in particular to use as control and interface circuitry for superconducting qubits, and eventually for a full scale quantum computer. The total heat load is moderate - current designs generate 0.5 /spl mu/W per bias resistor, so simple RSFQ integrated circuits are easily compatible with commercial helium dilution refrigerators, and this power can readily be reduced by several orders of magnitude for complex future designs - but thermal conductivity will be a bottleneck. We present a simple model of heat flow through standard RSFQ structures. We find that circuits designed for 4 K operation can be used with little or no modification below one Kelvin. At lower temperatures however the heat generated on chip cannot be removed, and the temperature of a working circuit will rise. We suggest fabrication design rule changes to address this problem.
Superconducting single flux quantum (SFQ) technology is well known for digital logic operations below 4.2 K, which are compatible with the Josephson junction qubit. Operation speed and signal sensitivity of circuits in SFQ are also sufficient to control qubits. Therefore, the SFQ circuit is a candidate technology for multiple qubit control. However, the self-heating effect of the SFQ circuit is a potential barrier to development of an SFQ-supported multiple qubit system because the qubit operating temperature is lower than the conventional 4.2 K. The multi-chip approach is a possible solution because the qubit chip can be thermally isolated from the SFQ circuitry. We report on recent progress in SFQ circuit and packaging technology for operation at sub-Kelvin temperatures. As for multi-chip module technology, a test sample of the multi-chip module shows good reliability of electrical connections between chips, and each solder bump has a bandwidth wide enough for signal transmission. We have designed lower power SFQ circuits for sub-Kelvin temperatures. The critical currents of Josephson junctions were scaled down, inductances were scaled up, and bias voltage was reduced to make power consumption lower. Based on our fabrication technology, critical current densities were optimized by considering trade-off relations between fabrication availability and operation speed. We successfully confirmed its correct operations at around 0.35 K. The combination of the multi-chip module and optimized SFQ circuits is very effective way of controlling qubit.
Abstract Superconductor logic families can operate with small power dissipation and are thus suitable as building blocks for various computing systems. In some applications, superconductor logic circuits should be designed using Josephson junctions with low I c values ( I c : critical current). For instance, lowering I c values enables qubit interface circuits to operate with very small power dissipation at ~10 mK and stochastic electronics to easily induce stochastic operations. In this study, we develop the AIST 1 kA cm −2 Nb planarized process (1KP) with a minimum critical current of 10 µA, dedicated to the design of qubit interface circuits and stochastic electronics. We also develop rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cell libraries using the 1KP. The power dissipation of RSFQ logic using the 1KP can be reduced to 3.2% of that for conventional RSFQ logic by reducing both I c values and a bias voltage. Furthermore, the amount of supply currents for AQFP circuits using the 1KP can be reduced to ~40% of that for conventional AQFP circuits due to a large mutual inductance between AQFP gates and excitation lines, which results from a reduction in I c and an increase in inductances. We demonstrate RSFQ and AQFP circuits fabricated by the 1KP at 4.2 K. These results indicate that RSFQ and AQFP circuits using the 1KP have the potential to be used for the design of qubit interface circuits and stochastic electronics.
Superconducting digital technology based on Rapid Single Flux Quantum logic (RSFQ) is a digital technology characterized by high speed, low power consumption and low operational temperatures. RSFQ is attractive for many applications and in particular for high frequency Digital Signal Processing (DSP) and for digital control of mK devices like superconducting qubits. Due to the 30 GHz clock speed, RSFQ DSP could be used to implement a Successive Interference Canceller for multi-user detection in a 3G wireless systems. The being developed DSP consists of a digital core, an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory and external semiconductor memory.The first part of this thesis is focusing on architecture and implementation of the hierarchical CMOS-RSFQ hybrid memory for the RSFQ DSP. The architecture ofthe RSFQ cache is optimized in order to reach the highest speed and reliable data communication with CMOS memory. Aspects of block synchronization betweenthe RSFQ cache and the RSFQ digital core are discussed and solved using a new developed RSFQ gate, C3. For design of different components of the DSP, a designapproach based on validated VHDL models is proposed and experimentally verified.The second part of this thesis is focusing on the design oflow-dissipative RSFQ circuits for interface to the superconducting qubits. Power dissipation ofRSFQ circuits is minimized. A low-temperature thermal model of resistively shunted Josephsonjunctions is developed and applied to optimize the shape of the shunt resistors in order to reduce their electron temperature. Depending on the available fabricationprocess the lowest noise temperature of RSFQ circuit can be in the range from 90 mK to 180 mK.
Rapid single-flux-quantum (RSFQ) technology has been proposed as control electronics for superconducting quantum bits because of the material and working temperature compatibility. In this work, we consider practical aspects of RSFQ circuit design for low noise low power operation. At the working temperature of 20 mK and operational frequency of 2 GHz, dissipated power per junction is reduced to 25 pW by using 6 µA critical current junctions available at the Hypres and VTT low J c fabrication process. To limit phonon temperature to 30 mK, a maximum of 40 junctions can be placed on a 5 mm × 5 mm chip. Electron temperature in resistive shunts of Josephson junctions is minimized by use of cooling fins, giving minimum electron temperatures of about 150 mK for the Hypres process and 70 mK for the VTT process.
Superconducting single-flux-quantum (SFQ) circuits have so far been developed and optimized for operation at or above helium temperatures. The SFQ approach, however, should also provide potentially viable and scalable control and readout circuits for Josephson-junction qubits and other applications with much lower, millikelvin, operating temperatures. This paper analyzes the overheating problem which becomes important in this temperature range. We suggest a thermal model of the SFQ circuits at subkelvin temperatures and present experimental results on overheating of electrons and silicon substrate which support this model. The model establishes quantitative limitations on the dissipated power both for “local” electron overheating in resistors and “global” overheating due to ballistic phonon propagation along the substrate. Possible changes in the thermal design of SFQ circuits in view of the overheating problem are also discussed.
As quantum computing processors increase in size, there is growing interest in developing cryogenic electronics to overcome significant challenges to system scaling. Single flux-quantum (SFQ) circuits offer a promising alternative to remote, bulky, and power-hungry room temperature electronics. To meet the need for digital qubit control, readout, and co-processing, SFQ circuits must be adapted to operate at millikelvin temperatures near quantum processors. SEEQC's SFQuClass digital quantum management approach proximally places energy-efficient SFQ (ERSFQ) circuits and qubits in a multi-chip module. This enables extremely low power dissipation, compatible with a typical dilution cryostat's limited cooling power, while maintaining high processing speed and low error rates. We report on systematic testing from 4 K to 10 mK of a comprehensive set of ERSFQ cells, as well as more complex circuits such as programmable counters and demultiplexers used in digital qubit control. We compare the operating margins and error rates of these circuits and find that, at millikelvin, bias margins decrease and the center of the margins (i.e., the optimal bias current value) increases by ~15%, compared to 4.2 K. The margins can be restored by thermal annealing by reducing Josephson junction (JJ) critical current Ic. To provide guidance for how circuit parameters vary from 4.2 K to millikelvin, relevant analog process control monitors (PCMs) were tested in the temperature range of interest. The measured JJ critical current (of the PCM JJ arrays) increases by ~15% when decreasing temperature from 4.2 K to millikelvin, in good agreement with both theory and the empirically measured change in the center of bias margins for the tested digital circuits.