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IEEE Transactions on Applied Superconductivity

Integration of cryocooled superconducting analog-to-digital converter and SiGe output amplifier

Deepnarayan Gupta, Alan M. Kadin, R.J. Webber, I. Rochwarger, D. Bryce, W.J. Hollander, Young Uk Yim, Channakeshav, R.P. Kraft, Jinwoo Kim, John F. McDonald

Published Jun 1, 2003• 25 citations
Publisher

Abstract

HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of RF lines and resistance of DC bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g., ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of high-speed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.

DOI
10.1109/tasc.2003.813911

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HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of RF lines and resistance of DC bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g., ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of high-speed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.
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We have demonstrated the full operation of digital RF receivers on a HYPRES-designed cryostat, which couples an Nb-based superconducting Rapid Single Flux Quantum (RSFQ) chip to a commercially available 100 mW 4 Kelvin Gifford-McMahon cryocooler. A field demonstration of digitization of a satellite-received signal at 7.7 GHz is described. The digital receiver chip is a 1 cm×1 cm chip comprising ∼11,000 Josephson junctions (JJ). The measured cryogenic thermal and magnetic environments of the chip are discussed and their impact on performance. Reception and direct digital conversion of real signals in the HF-, VHF-, and X-bands including signals from military satellite antennae shows the potential of this system to replace large and power-hungry multiple analog receivers.
Wireless applications would be less expensive, more flexible, and more robust if they had more digital and less analog circuitry. The problem is implementing digital signal processing at radio frequencies. Conventional data converters (ADCs and DACs) and digital circuits are simply not fast enough. However, superconductors can provide ultra fast mixed signal and digital circuits with the linearity and dynamic range required for true direct, digital-RF processing. These superconducting circuits are digital ICs based on Josephson junctions and "rapid-single-flux-quantum" logic (RSFQ), where switching speeds up to 750 GHz have been demonstrated enabling true digital-RF architecture at clock speeds eventually up to 160 GHz. This permits direct conversion between analog RF and digital baseband signals, replacing frequency and protocol-specific analog hardware with flexible digital processors. Data conversion in high frequency wireless applications at frequencies up to 50 GHz will soon become practical. Hypres recently delivered a HF-VHF all digital RF receiver (ADR) prototype to ONR. Testing of this ADR has demonstrated the superior performance of superconducting ICs in cryocooled systems. A US Navy laboratory is now evaluating the world's first complete prototype digital RF receiver capable of direct digitization from DC to 2 GHz
Future development of superconductor digital and mixed-signal ICs requires extensive testing with a large number of input/output (I/O) lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. There is a growing need for a standardized test apparatus for a variety of complex superconducting chips and multichip modules (MCMs). Such a test apparatus must support many I/O lines, be easy and cost-effective to operate, and support prolonged automated testing. Existing test apparatus include liquid He cryoprobes and cryocooled custom digital-RF systems, both of which have drawbacks. Liquid He cryoprobes with universal wiring, such as 40 or 80 coaxial cables, are convenient to use. Cooled by immersion in a tank filled with liquid He, these cryoprobes allow rapid cool-down and warm-up. However, large consumption of liquid He, the cost of which has been steadily increasing worldwide, makes this solution rather expensive and wasteful. On the other hand, one can exploit the modular reconfigurability of HYPRES' digital-RF receiver product to create a testbed for different ICs. Such a system uses the smallest commercially available closed-cycle refrigerator (~1.2 kW) and has negligible operating cost. However, reconfiguration takes time and expertise since these products are specially designed with customized chip package and wiring to minimize the thermal load on the cryocooler. These low-maintenance systems are ideal for prolonged operation of a single chip, which is invaluable for superconductor electronics system developers and end-users. The integrated cryoelectronics testbed (ICE-T) combines the advantages of the liquid He cryoprobe and the cryocooled digital-RF product. By using a more powerful, commercially available, electrically powered closed-cycle refrigerator (7 kW), ICE-T alleviates the thermal constraints on wiring while maintaining very low operating cost. By separating the electrical and thermal subsystems, it maintains modularity without sacrificing the universality of the cryoprobe. A set of universal and custom electrical modules can be independently built and inserted in ICE-T. Universal inserts with 40 and 80 coaxial cables accommodate all chips with standard I/O pads like the familiar liquid He cryoprobes. Custom inserts for different classes of chips and MCMs are designed and built according to user requirements and specifications. The utility of the ICE-T was successfully demonstrated by testing a benchmark superconducting digital circuit at low frequency and an analog-to-digital converter chip clocked above 20 GHz.
Superconducting micro-electronics (SME) technology is capable of realizing extremely high speed digital receivers performing direct digitization of microwave signals with very low power consumption. SME technology uses integrated circuits based on Josephson junctions and rapid single-flux quantum (RSFQ) logic operating at 4°K. The analogue-to-digital converter (ADC) is a basic building block of such receivers. Quantization and sampling are two fundamental parts of ADCs. Flash ADCs are the fastest converters and consist of comparators and a resistor network. \nThis thesis investigates the use of a multi-layer niobium-based low-temperature superconducting process to implement a resistor network. Several configurations for resistors are investigated both electrically and thermally. The resistors are designed to maintain their values from DC to 50GHz. Floating metal structures are added and optimized to minimize the inductance of the structure in order to obtain frequency-independent resistors over a frequency range of 50GHz. Several resistors and R-2R ladder networks are fabricated in the same process and measured in an RF cryogenic probe station at the Centre for Integrated RF Engineering (CIRFE) Lab at the University of Waterloo. Theoretical thermal analysis, is also carried out for these resistors to investigate temperature variations through the structures when operating at different power levels. The investigation is important for making sure that the resistors’ dissipated heat does not raise the local temperature above the transition temperature of niobium.