OPERATION OF SUPERCONDUCTING DIGITAL RECEIVER CIRCUITS ON 2-STAGE GIFFORD-MCMAHON CRYOCOOLER
Robert J. Webber, Vladimir Valentinovich Dotsenko, Andrei Talalaevskii, Robert Miller, Jia Tang, Dmitri E. Kirichenko, I. V. Vernik, Pavel Shevchenko, V. Borzenets, Deepnarayan Gupta, Oleg A. Mukhanov, John G Weisend, John Barclay, Susan R. Breon, Jonathan A. Demko, Michael DiPirro, J. Patrick Kelley, Peter Kittel, Arkadiy Klebaner, Al Zeller, Mark Zagarola, Steven Van Sciver, Andrew M. Rowe, John M. Pfotenhauer, Tom Peterson, Jennifer Lock
We have demonstrated the full operation of digital RF receivers on a HYPRES-designed cryostat, which couples an Nb-based superconducting Rapid Single Flux Quantum (RSFQ) chip to a commercially available 100 mW 4 Kelvin Gifford-McMahon cryocooler. A field demonstration of digitization of a satellite-received signal at 7.7 GHz is described. The digital receiver chip is a 1 cm×1 cm chip comprising ∼11,000 Josephson junctions (JJ). The measured cryogenic thermal and magnetic environments of the chip are discussed and their impact on performance. Reception and direct digital conversion of real signals in the HF-, VHF-, and X-bands including signals from military satellite antennae shows the potential of this system to replace large and power-hungry multiple analog receivers.
We have demonstrated the full operation of digital RF receivers on a HYPRES-designed cryostat, which couples an Nb-based superconducting Rapid Single Flux Quantum (RSFQ) chip to a commercially available 100 mW 4 Kelvin Gifford-McMahon cryocooler. A field demonstration of digitization of a satellite-received signal at 7.7 GHz is described. The digital receiver chip is a 1 cm×1 cm chip comprising ∼11,000 Josephson junctions (JJ). The measured cryogenic thermal and magnetic environments of the chip are discussed and their impact on performance. Reception and direct digital conversion of real signals in the HF-, VHF-, and X-bands including signals from military satellite antennae shows the potential of this system to replace large and power-hungry multiple analog receivers.
Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ∼30GHz clock frequencies.
Wireless applications would be less expensive, more flexible, and more robust if they had more digital and less analog circuitry. The problem is implementing digital signal processing at radio frequencies. Conventional data converters (ADCs and DACs) and digital circuits are simply not fast enough. However, superconductors can provide ultra fast mixed signal and digital circuits with the linearity and dynamic range required for true direct, digital-RF processing. These superconducting circuits are digital ICs based on Josephson junctions and "rapid-single-flux-quantum" logic (RSFQ), where switching speeds up to 750 GHz have been demonstrated enabling true digital-RF architecture at clock speeds eventually up to 160 GHz. This permits direct conversion between analog RF and digital baseband signals, replacing frequency and protocol-specific analog hardware with flexible digital processors. Data conversion in high frequency wireless applications at frequencies up to 50 GHz will soon become practical. Hypres recently delivered a HF-VHF all digital RF receiver (ADR) prototype to ONR. Testing of this ADR has demonstrated the superior performance of superconducting ICs in cryocooled systems. A US Navy laboratory is now evaluating the world's first complete prototype digital RF receiver capable of direct digitization from DC to 2 GHz
Wireless applications would be less expensive, more flexible, and more robust if they had more digital and less analog circuitry. The problem is implementing digital signal processing at radio frequencies. Conventional data converters (ADCs and DACs) and digital circuits are simply not fast enough, especially at SATCOM frequencies. However, superconductors can provide ultra fast mixed signal and digital circuits with the linearity and dynamic range required for true direct, digital-RF processing. These superconducting circuits are digital ICs based on Josephson junctions and "rapid-single-flux-quantum" logic (RSFQ), where simple circuit switching speeds up to 750 GHz have been demonstrated. This permits direct conversion between analog RF and digital baseband signals, replacing frequency and protocol-specific analog hardware with flexible digital processors. HYPRES recently developed and delivered an X-band All Digital RF Receiver (XADR) prototype system for the US Army CERDEC and PM DCATS. The concept of this ADR is to replace the entire analog RF receive chain between the antenna and the baseband demodulator with a high performance digital RF equivalent. The first XADR prototype system has been successfully demonstrated at the Joint SATCOM engineering Center (JSEC). End to end link testing, over the satellite has been successfully completed using an existing AN/GSC-39 X-band earth terminal, an XTAR satellite, the X-band ADR and a SATCOM modem.
HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of RF lines and resistance of DC bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g., ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of high-speed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.
HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency. The complete system, consisting of a cryopackaged Nb superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field-programmable gate array (FPGA) based post-processing module, has been developed. Depending on the targeted application the ADR chip comprised either a low-pass delta with phase modulation-demodulation architecture or X-band band-pass sigma-delta modulators together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chips were fabricated using a 4.5-kA/cm2HYPRES process and were cryopackaged using a commercial-off-the-shelf cryocooler. Recently, with significant improvements in chip cryopackage, room-temperature electronics and FPGA programming we were able to achieve stable operation of a low-pass ADR at 28.16 GHz and X-band ADR at 30.72 GHz clock frequencies. Experimental results are presented and discussed.
AbstractSuperconducting digital technology based on Rapid Single Flux Quantum (RSFQ) logic offers a 50 times faster clock rate and 100 times less on chip power consumption than today's mainstream semiconductor electronics. This technology is attractive for many applications and in particular for Digital Signal Processing (DSP). The applications of the RSFQ DSPs are numerous and include multi-user detection in spread spectrum system, channel equalization for Multi-in, Multi-out (MIMO) systems, and blind detection and signal tracking for signal intelligence.At Chalmers we are developing a hybrid DSP with target performance of 30 giga operations per second. It consists of an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory, and an external semiconductor memory. The development of the complex high speed cryogenic digital system requires interface, packaging and testing solutions. The main difficulties are due to the 4 K operational temperature, the high magnetic field sensitivity of the RSFQ circuits, the multi-channel high bandwidth interface required in the hybrid architecture, and the high speed RSFQ digital core. The key steps towards addressing each of these problems are the subject of this thesis. The main emphasis is put on the experimental testing and interfacing of superconductor electronics. A large part of the work is connected to the experimental verification of DSP components and their incremental improvement towards functionality. The RSFQ circuits tested were fabricated using the four-metal layer VLSI processes available from NGST(8 kA/cm^2 Josephson junction critical current) and HYPRES (both 1 kA/cm^2 and HYPRES 4.5 kA/cm^2. The main results of the work are demonstrations of the RSFQ cache memory with more than 2,000 Josephson junctions, 33.5 GHz operation of the digital clock controller, and 20.48 GHz operation of the autocorrelator. In addition, various experiments have been done for investigation of parasitic effects in RSFQ circuits such as flux trapping and influence of the high current bias lines.At the final stage of the work, a unique high bandwidth 4 K cryocooler based experimental setup has been developed. The system, developed in close cooperation with Hypres Inc. USA, has 40 high speed I/Os with bandwidth of 2 Gbps, 64 DC bias channels, 4 high frequency clock lines, and 4 auxiliary control lines. It supports exchangeable test units for 10 mm x 10 mm and 20 mm x 20 mm Multi Chip Module (MCM) carriers. The availability of such a system is critical to demonstration of the hybrid DSP prototype and future commercialization.