IEEE Transactions on Applied Superconductivity

Progress in the Development of Cryocooled Digital Channelizing RF Receivers

I. V. Vernik, Dmitri E. Kirichenko, Vladimir Valentinovich Dotsenko, Robert J. Webber, Robert Miller, Pavel Shevchenko, Deepnarayan Gupta

Published Jun 1, 2009• 14 citations

Publisher

Abstract

HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency. The complete system, consisting of a cryopackaged Nb superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field-programmable gate array (FPGA) based post-processing module, has been developed. Depending on the targeted application the ADR chip comprised either a low-pass delta with phase modulation-demodulation architecture or X-band band-pass sigma-delta modulators together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chips were fabricated using a 4.5-kA/cm2HYPRES process and were cryopackaged using a commercial-off-the-shelf cryocooler. Recently, with significant improvements in chip cryopackage, room-temperature electronics and FPGA programming we were able to achieve stable operation of a low-pass ADR at 28.16 GHz and X-band ADR at 30.72 GHz clock frequencies. Experimental results are presented and discussed.

DOI: 10.1109/tasc.2009.2018424

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