HYPRES, Inc has successfully completed the development of the first-generation superconductor digital channelizing receiver. This channelizer circuit, comprising a single-bit digital in-phase and quadrature (I&Q) mixer and two second-order digital decimation filters (DDFs), was built with rapid single flux quantum (RSFQ) logic. The further development of digital-RF receivers requires a multi-bit (n × k) multiplier for digital mixing of n-bit data streams provided by advanced low pass or band pass modulator and k-bit digital local oscillator (LO). We report our results on the design of both n × 1-bit and 1 × k-bit mixers where either data or LO streams can have a multi-bit representation. The reported approach is the generalization of a 1 × 1-bit mixer used in the first-generation channelizer. The detailed block-diagrams are given for both types and the correct operation at low frequency of test chips with 3-bit mixers are reported. Design issues pertaining to scaling to a digital-RF receiver containing multi-bit mixers are discussed.
HYPRES, Inc has successfully completed the development of the first-generation superconductor digital channelizing receiver. This channelizer circuit, comprising a single-bit digital in-phase and quadrature (I&Q) mixer and two second-order digital decimation filters (DDFs), was built with rapid single flux quantum (RSFQ) logic. The further development of digital-RF receivers requires a multi-bit (n × k) multiplier for digital mixing of n-bit data streams provided by advanced low pass or band pass modulator and k-bit digital local oscillator (LO). We report our results on the design of both n × 1-bit and 1 × k-bit mixers where either data or LO streams can have a multi-bit representation. The reported approach is the generalization of a 1 × 1-bit mixer used in the first-generation channelizer. The detailed block-diagrams are given for both types and the correct operation at low frequency of test chips with 3-bit mixers are reported. Design issues pertaining to scaling to a digital-RF receiver containing multi-bit mixers are discussed.
We have developed and experimentally demonstrated several new RSFQ circuits, designed as components for digital receivers that are being developed by HYPRES. The first circuit is a digital phase generator, which produces a periodic digital signal with a controllable phase shift. This signal is obtained by decimation of an external high frequency signal by a factor of 1024, and provides a controllable phase shift with digital precision of /spl pi//512. The second circuit, a precise digital static frequency divider, is capable of dividing of an input signal frequency by any integer value between 1 and 1024. The third circuit is a digital quadrature mixer performing digital downconversion of bit-stream data. This report presents results of experimental evaluation of these circuits at speeds in excess of 30 GHz.
Superconductive technology offers unparalleled digital and mixed-signal circuit performance, advancing digital processing from baseband to RF stages. This allows elimination of analog filters and mixers with generally poorly controlled phase performance, causing intersymbol interference limiting an overall communication system performance. HYPRES has been developing superconducting circuit components for application to digital RF communication transceivers. The components include low-pass and band-pass analog-to-digital converters, digital decimation and correlation-based filters, digital up/down-converters, and low-time-jitter clock sources. All of these are based on ultra-fast Rapid Single Flux Quantum (RSFQ) digital circuits, with clock rates up to 20 GHz demonstrated with 3-micron technology, and being scaled to 40 GHz and above. In this paper, we will discuss design and performance of some of these components. 1.
HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency. The complete system, consisting of a cryopackaged Nb superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field-programmable gate array (FPGA) based post-processing module, has been developed. Depending on the targeted application the ADR chip comprised either a low-pass delta with phase modulation-demodulation architecture or X-band band-pass sigma-delta modulators together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chips were fabricated using a 4.5-kA/cm2HYPRES process and were cryopackaged using a commercial-off-the-shelf cryocooler. Recently, with significant improvements in chip cryopackage, room-temperature electronics and FPGA programming we were able to achieve stable operation of a low-pass ADR at 28.16 GHz and X-band ADR at 30.72 GHz clock frequencies. Experimental results are presented and discussed.
Wireless applications would be less expensive, more flexible, and more robust if they had more digital and less analog circuitry. The problem is implementing digital signal processing at radio frequencies. Conventional data converters (ADCs and DACs) and digital circuits are simply not fast enough, especially at SATCOM frequencies. However, superconductors can provide ultra fast mixed signal and digital circuits with the linearity and dynamic range required for true direct, digital-RF processing. These superconducting circuits are digital ICs based on Josephson junctions and "rapid-single-flux-quantum" logic (RSFQ), where simple circuit switching speeds up to 750 GHz have been demonstrated. This permits direct conversion between analog RF and digital baseband signals, replacing frequency and protocol-specific analog hardware with flexible digital processors. HYPRES recently developed and delivered an X-band All Digital RF Receiver (XADR) prototype system for the US Army CERDEC and PM DCATS. The concept of this ADR is to replace the entire analog RF receive chain between the antenna and the baseband demodulator with a high performance digital RF equivalent. The first XADR prototype system has been successfully demonstrated at the Joint SATCOM engineering Center (JSEC). End to end link testing, over the satellite has been successfully completed using an existing AN/GSC-39 X-band earth terminal, an XTAR satellite, the X-band ADR and a SATCOM modem.
Abstract: We have developed and experimentally evaluated at high-speed, a complete set of arithmetic circuits (multiply, add, and accumulate) for high performance digital signal processing (DSP). These circuits take advantage of the unique features of the Rapid Single-Flux Quantum (RSFQ) logic/memory family, including fusion of logic and memory functions at the gate level, pulse representation of clock and data, and the ability to maintain inter cell propagation delays using Josephson transmission lines (JTLs). The circuits developed have been successfully used in the implementation of a serial radix 2 butterfly, a decimation digital filter, and of an arithmetic unit for digital beam forming. The 8×8-bit RSFQ multiplier uses a two- level parallel carry- save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave pipelined [4:2] compressors built with toggle flip-flop cells.
Reduction of total bias current using the serial biasing technique is required for RSFQ-based digital-RF receiver realization. This will have a major impact on reducing the size, weight and power consumption of the complete cryocooled receiver system. The approach is based on partitioning a homogeneous design into several isolated islands biased in series and transmitting SFQ pulses between islands, over moats through inductively-coupled driver-receiver-pairs (DRPs). Experimental data on testing of 100 DRPs connected in series are reported and bit-error-rate estimates are given. Our goal is to serially bias two sets of homogeneous circuit blocks in the digital-RF receiver design: (1) digital decimation filter (DDF) bit slices, and (2) output drivers. The correct operation of test chips containing four bit-slices of a second-order DDF, partitioned into 2 and 4 islands, are demonstrated. Results of 8 output drivers, serially biased on 2, 4, and 8 islands, are reported. Design issues of scaling to a digital-RF receiver, containing 18-20 DDF bit slices and 16 output drivers are discussed.