We have developed and experimentally demonstrated several new RSFQ circuits, designed as components for digital receivers that are being developed by HYPRES. The first circuit is a digital phase generator, which produces a periodic digital signal with a controllable phase shift. This signal is obtained by decimation of an external high frequency signal by a factor of 1024, and provides a controllable phase shift with digital precision of /spl pi//512. The second circuit, a precise digital static frequency divider, is capable of dividing of an input signal frequency by any integer value between 1 and 1024. The third circuit is a digital quadrature mixer performing digital downconversion of bit-stream data. This report presents results of experimental evaluation of these circuits at speeds in excess of 30 GHz.
We have developed and experimentally demonstrated several new RSFQ circuits, designed as components for digital receivers that are being developed by HYPRES. The first circuit is a digital phase generator, which produces a periodic digital signal with a controllable phase shift. This signal is obtained by decimation of an external high frequency signal by a factor of 1024, and provides a controllable phase shift with digital precision of /spl pi//512. The second circuit, a precise digital static frequency divider, is capable of dividing of an input signal frequency by any integer value between 1 and 1024. The third circuit is a digital quadrature mixer performing digital downconversion of bit-stream data. This report presents results of experimental evaluation of these circuits at speeds in excess of 30 GHz.
Superconductive technology offers unparalleled digital and mixed-signal circuit performance, advancing digital processing from baseband to RF stages. This allows elimination of analog filters and mixers with generally poorly controlled phase performance, causing intersymbol interference limiting an overall communication system performance. HYPRES has been developing superconducting circuit components for application to digital RF communication transceivers. The components include low-pass and band-pass analog-to-digital converters, digital decimation and correlation-based filters, digital up/down-converters, and low-time-jitter clock sources. All of these are based on ultra-fast Rapid Single Flux Quantum (RSFQ) digital circuits, with clock rates up to 20 GHz demonstrated with 3-micron technology, and being scaled to 40 GHz and above. In this paper, we will discuss design and performance of some of these components. 1.
HYPRES, Inc has successfully completed the development of the first-generation superconductor digital channelizing receiver. This channelizer circuit, comprising a single-bit digital in-phase and quadrature (I&Q) mixer and two second-order digital decimation filters (DDFs), was built with rapid single flux quantum (RSFQ) logic. The further development of digital-RF receivers requires a multi-bit (n × k) multiplier for digital mixing of n-bit data streams provided by advanced low pass or band pass modulator and k-bit digital local oscillator (LO). We report our results on the design of both n × 1-bit and 1 × k-bit mixers where either data or LO streams can have a multi-bit representation. The reported approach is the generalization of a 1 × 1-bit mixer used in the first-generation channelizer. The detailed block-diagrams are given for both types and the correct operation at low frequency of test chips with 3-bit mixers are reported. Design issues pertaining to scaling to a digital-RF receiver containing multi-bit mixers are discussed.
Wireless applications would be less expensive, more flexible, and more robust if they had more digital and less analog circuitry. The problem is implementing digital signal processing at radio frequencies. Conventional data converters (ADCs and DACs) and digital circuits are simply not fast enough. However, superconductors can provide ultra fast mixed signal and digital circuits with the linearity and dynamic range required for true direct, digital-RF processing. These superconducting circuits are digital ICs based on Josephson junctions and "rapid-single-flux-quantum" logic (RSFQ), where switching speeds up to 750 GHz have been demonstrated enabling true digital-RF architecture at clock speeds eventually up to 160 GHz. This permits direct conversion between analog RF and digital baseband signals, replacing frequency and protocol-specific analog hardware with flexible digital processors. Data conversion in high frequency wireless applications at frequencies up to 50 GHz will soon become practical. Hypres recently delivered a HF-VHF all digital RF receiver (ADR) prototype to ONR. Testing of this ADR has demonstrated the superior performance of superconducting ICs in cryocooled systems. A US Navy laboratory is now evaluating the world's first complete prototype digital RF receiver capable of direct digitization from DC to 2 GHz
A low-skew frequency divider and clock controller have been designed for high-frequency timing of superconductor rapid single-flux-quantum (RSFQ) digital systems. The circuits have only about 10-ps skew between input and output signals and are applicable for multirate digital systems (e,g., oversampling analog-to-digital converter and bit-serial digital systems). Several circuits have been fabricated in conventional Nb-trilayer technology with a critical current density of 1 kA/cm/sup 2/. The most complex clock controller generates trains of 2/sup 24/ single-flux-quantum pulses with a period of less than 70 ps. The long-term relative stability of these intervals has been measured to be better than 6/spl times/10/sup -5/. The basic component of the controller, a frequency divider, operates at input frequencies above 85 GHz.>
AbstractSuperconducting digital technology based on Rapid Single Flux Quantum (RSFQ) logic offers a 50 times faster clock rate and 100 times less on chip power consumption than today's mainstream semiconductor electronics. This technology is attractive for many applications and in particular for Digital Signal Processing (DSP). The applications of the RSFQ DSPs are numerous and include multi-user detection in spread spectrum system, channel equalization for Multi-in, Multi-out (MIMO) systems, and blind detection and signal tracking for signal intelligence.At Chalmers we are developing a hybrid DSP with target performance of 30 giga operations per second. It consists of an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory, and an external semiconductor memory. The development of the complex high speed cryogenic digital system requires interface, packaging and testing solutions. The main difficulties are due to the 4 K operational temperature, the high magnetic field sensitivity of the RSFQ circuits, the multi-channel high bandwidth interface required in the hybrid architecture, and the high speed RSFQ digital core. The key steps towards addressing each of these problems are the subject of this thesis. The main emphasis is put on the experimental testing and interfacing of superconductor electronics. A large part of the work is connected to the experimental verification of DSP components and their incremental improvement towards functionality. The RSFQ circuits tested were fabricated using the four-metal layer VLSI processes available from NGST(8 kA/cm^2 Josephson junction critical current) and HYPRES (both 1 kA/cm^2 and HYPRES 4.5 kA/cm^2. The main results of the work are demonstrations of the RSFQ cache memory with more than 2,000 Josephson junctions, 33.5 GHz operation of the digital clock controller, and 20.48 GHz operation of the autocorrelator. In addition, various experiments have been done for investigation of parasitic effects in RSFQ circuits such as flux trapping and influence of the high current bias lines.At the final stage of the work, a unique high bandwidth 4 K cryocooler based experimental setup has been developed. The system, developed in close cooperation with Hypres Inc. USA, has 40 high speed I/Os with bandwidth of 2 Gbps, 64 DC bias channels, 4 high frequency clock lines, and 4 auxiliary control lines. It supports exchangeable test units for 10 mm x 10 mm and 20 mm x 20 mm Multi Chip Module (MCM) carriers. The availability of such a system is critical to demonstration of the hybrid DSP prototype and future commercialization.
Wireless applications would be less expensive, more flexible, and more robust if they had more digital and less analog circuitry. The problem is implementing digital signal processing at radio frequencies. Conventional data converters (ADCs and DACs) and digital circuits are simply not fast enough, especially at SATCOM frequencies. However, superconductors can provide ultra fast mixed signal and digital circuits with the linearity and dynamic range required for true direct, digital-RF processing. These superconducting circuits are digital ICs based on Josephson junctions and "rapid-single-flux-quantum" logic (RSFQ), where simple circuit switching speeds up to 750 GHz have been demonstrated. This permits direct conversion between analog RF and digital baseband signals, replacing frequency and protocol-specific analog hardware with flexible digital processors. HYPRES recently developed and delivered an X-band All Digital RF Receiver (XADR) prototype system for the US Army CERDEC and PM DCATS. The concept of this ADR is to replace the entire analog RF receive chain between the antenna and the baseband demodulator with a high performance digital RF equivalent. The first XADR prototype system has been successfully demonstrated at the Joint SATCOM engineering Center (JSEC). End to end link testing, over the satellite has been successfully completed using an existing AN/GSC-39 X-band earth terminal, an XTAR satellite, the X-band ADR and a SATCOM modem.