IEEE Transactions on Applied Superconductivity

Serially Biased Components for Digital-RF Receiver

Timur V. Filippov, Anubhav Sahu, Saad M. Sarwana, Deepnarayan Gupta, Vasili K. Semenov

Published Jun 1, 2009• 26 citations

Abstract

Reduction of total bias current using the serial biasing technique is required for RSFQ-based digital-RF receiver realization. This will have a major impact on reducing the size, weight and power consumption of the complete cryocooled receiver system. The approach is based on partitioning a homogeneous design into several isolated islands biased in series and transmitting SFQ pulses between islands, over moats through inductively-coupled driver-receiver-pairs (DRPs). Experimental data on testing of 100 DRPs connected in series are reported and bit-error-rate estimates are given. Our goal is to serially bias two sets of homogeneous circuit blocks in the digital-RF receiver design: (1) digital decimation filter (DDF) bit slices, and (2) output drivers. The correct operation of test chips containing four bit-slices of a second-order DDF, partitioned into 2 and 4 islands, are demonstrated. Results of 8 output drivers, serially biased on 2, 4, and 8 islands, are reported. Design issues of scaling to a digital-RF receiver, containing 18-20 DDF bit slices and 16 output drivers are discussed.

DOI: 10.1109/tasc.2009.2018426

Related papers

Pulse Interfaces and Current Management Techniques for Serially Biased RSFQ Circuits

Ashish Shukla, Dmitri E. Kirichenko, Timur V. Filippov +4 more

As digital superconductor circuits based on Rapid Single Flux Quantum (RSFQ) logic scale up in complexity, so does the total current required to provide dc bias. Serial biasing (SB) is a promising solution that can be used to reduce the current by placing identical digital blocks on islands with isolated grounds and bias them sequentially. There are typically two implementations that are essential for the SB approach: the design of a driver-receiver pair (DRP) for inter-island pulse transport and the current management technique to handle the bias current flowing into and out of an island. While a DRP with good fidelity is essential for any serially biased circuit, the current management becomes critical for designs with relatively large bias current. In this paper, we address the latter. First, we propose a grapevine biasing scheme for serial bias current management. Second, we implement the technique using two exemplar circuits: the parallel counter and the digital decimation filter. We report the low and high speed test results up to 50 GHz for both circuits fabricated at MIT-LL in the SFQ5ee 10 kA/2 Ω fab node.

IEEE Transactions on Applied SuperconductivityJan 13, 20229 citations

60-GHz Single Flux Quantum Pulse Transfer Circuit for Serial Biasing

Ashish Shukla, Dmitri E. Kirichenko, Timur V. Filippov +4 more

Serial Biasing (SB) is a technique to reduce the total DC bias current of Rapid Single Flux Quantum (RSFQ) circuits by partitioning a design into several islands with isolated grounds and sequential biasing. In this paper we focus on the design of a driver-receiver pair (DRP) to transfer pulses between islands that are galvanically isolated for pulse streams. We discuss both DRP itself and the structure for its testing, that comprises several DRPs connected in series, on-chip pseudo random binary sequence (PRBS) generator for circuit stimulation, and HF output interface. We use the layout of DRPs’ chain as an example to illustrate the advantage of the grapevine (GV) approach, introduced earlier, to manage the bias current flowing into and out of an island. The GV current management technique is analyzed by both electromagnetic simulations and measurement, compared, and contrasted with the so-called ‘straightforward’ (SF) approach. The maximum operational frequency for SF test structure was 10 GHz with zero margins for the SB current. Measurements of the GV structure at 10 GHz demonstrated BER of 10−12with ±5.8% margins for SB current. We observed the correct operation of the 5-island DRP chain up to 60 GHz using the grapevine approach for SB current management. All chips were fabricated at MIT Lincoln Laboratory using SFQ5ee fab node.

IEEE Transactions on Applied SuperconductivityJan 23, 20235 citations

Serial Biasing Technique for Electronic Design Automation in RSFQ Circuits

Ashish Shukla, Timur V. Filippov, Dmitri E. Kirichenko +4 more

There has been renewed interest and efforts in increasing the complexity of superconductor circuits by means of electronic design automation (EDA). Serial biasing (SB) is a technique that reduces the total dc bias current required by large rapid single flux quantum (RSFQ) circuits, including its energy-efficient variant, ERSFQ. We believe SB needs to be incorporated in any EDA flow for large circuits. In SB, equally biased circuit blocks are placed on galvanically isolated islands and biased in series. SFQ pulses are transferred between islands by means of driver-receiver pairs (DRPs). The special current management technique, called the grapevine (GV) approach and introduced earlier, is used to handle the bias current flowing in and out of an island. In this article, we present all required layout primitives needed to implement SB for the IARPA-led SuperTools cell library that targets the SFQ5ee fab node at MIT Lincoln Laboratory. We discuss the horizontal and vertical composite driver-receiver pairs that comprise not only DRPs but also transmitters and receivers for passive transmission lines. We present the basic blocks to implement the GV managing technique for current injection and extraction. As a proof of concept, we designed a four-island test circuit that comprises all discussed layout primitives and employs an on-chip pseudorandom binary sequence generator as a test pattern source. The test circuit worked up to 50 GHz at the BER level of 10−12. We discuss future steps to improve the SB technique.

IEEE Transactions on Applied SuperconductivityOct 14, 20224 citations

Current recycling and SFQ signal transfer in large scale RSFQ circuits

H. Kang, Steven B. Kaplan

The practical implementation of RSFQ technology in most digital electronics application areas requires much more complexity than the presently developed circuits. There are two important issues in building large-scale RSFQ circuits: 1) the recycling of the bias currents and 2) the transfer of SFQ pulses between circuits located far apart. RSFQ circuits are well known to operate with DC current bias. Even though the DC current biasing is more forgiving than the problematic AC biasing, it can still be a big concern when the circuit size becomes large. Dramatic reduction of the total bias current can be achieved by biasing several RSFQ circuits in series, where each circuit is positioned on a separate ground plane. In this work, we have used magnetically coupled Josephson transmission lines as inputs and outputs of an isolated shift register to show the feasibility of using the concept of serial biasing in current recycling. The circuit was simulated, fabricated with Nb technology, and tested at a temperature of 4.2 K. Test results show that SFQ pulses were transferred into the shift register built on a separate ground plane, clocked through it, and sent out back to the circuit on the original ground plane. We also studied on how to transfer SFQ pulses over an extended length, an important issue in building large RSFQ circuits. We have designed the circuits to test our microstrip line and multichip module approaches. We designed, optimized, fabricated and tested the circuits. Test results show that SFQ pulses can be successfully transmitted over an extensive distance in a chip and between chips.

IEEE Transactions on Applied SuperconductivityJun 1, 200358 citations

Multi-Bit Mixers for Digital-RF Receivers

Timur V. Filippov, Saad M. Sarwana, Anubhav Sahu +2 more

HYPRES, Inc has successfully completed the development of the first-generation superconductor digital channelizing receiver. This channelizer circuit, comprising a single-bit digital in-phase and quadrature (I&Q) mixer and two second-order digital decimation filters (DDFs), was built with rapid single flux quantum (RSFQ) logic. The further development of digital-RF receivers requires a multi-bit (n × k) multiplier for digital mixing of n-bit data streams provided by advanced low pass or band pass modulator and k-bit digital local oscillator (LO). We report our results on the design of both n × 1-bit and 1 × k-bit mixers where either data or LO streams can have a multi-bit representation. The reported approach is the generalization of a 1 × 1-bit mixer used in the first-generation channelizer. The detailed block-diagrams are given for both types and the correct operation at low frequency of test chips with 3-bit mixers are reported. Design issues pertaining to scaling to a digital-RF receiver containing multi-bit mixers are discussed.

IEEE Transactions on Applied SuperconductivityDec 14, 20102 citations

Current Recycling: New Results

Vasili K. Semenov, Yuri A. Polyakov

Long ago, current recycling or serial biasing technique was recognized as a promising solution for the reduction of bias current in VLSI dc biased digital superconductor circuits. Despite a significant number of declarations, not so many successful experiments have been reported so far. In the paper we discuss our recent experiments with serially biased 16-bit counter-flow RSFQ shift registers, connected by special interfaces that are able to transfer SFQ pulses between the galvanically isolated driver and receiver. The required functionality is achieved using a superconductor transformer with isolated input and output coils. The known drawback of such interfaces is their parasitic sensitivity to magnetic fields induced by remote currents. To depress this sensitivity we have implemented a special superconductor guard that uses six superconductor layers. We have achieved stable operations of such registers with 16 current recycling stacks. The circuits have been fabricated at MIT Lincoln Laboratory.

IEEE Transactions on Applied SuperconductivityMar 18, 201915 citations