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IEEE Transactions on Applied Superconductivity

Minimization of Parasitic Inductances in SFQ Circuits Using Over- and Under-Ground Planes

Hiroaki Myoren, N. Kishita, Tohru Taino, S. Takada

Published Jun 1, 2007• 3 citations
Publisher

Abstract

We designed the single-flux-quantum (SFQ) circuits that were fabricating using the NEC 2.5 kA/cm2standard process that has four Nb layers. Before designing circuits with two ground planes, we estimated sheet inductances of the base and counter planes using simple rectangular-shape inductors. Estimated sheet inductance of the base plane was 0.75 of the original value for the circuits with only under-ground plane. For the counter plane, sheet inductance was estimated to be 0.55 of the original value. We designed a 2-branch D-FF gate and fabricated SFQ circuits including the 2-branch D-FF using the NEC standard process. Parasitic inductances of the counter layer in the 2-branch D-FF were effectively minimized using two ground planes and frequency dependences of the lower bias margin were improved.

DOI
10.1109/tasc.2007.898053

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We designed the single-flux-quantum (SFQ) circuits that were fabricating using the NEC 2.5 kA/cm2standard process that has four Nb layers. Before designing circuits with two ground planes, we estimated sheet inductances of the base and counter planes using simple rectangular-shape inductors. Estimated sheet inductance of the base plane was 0.75 of the original value for the circuits with only under-ground plane. For the counter plane, sheet inductance was estimated to be 0.55 of the original value. We designed a 2-branch D-FF gate and fabricated SFQ circuits including the 2-branch D-FF using the NEC standard process. Parasitic inductances of the counter layer in the 2-branch D-FF were effectively minimized using two ground planes and frequency dependences of the lower bias margin were improved.
We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (IC), bias current (Ibias), and inductance satisfied minimal margin requirements. Critical margins of ICand Ibiaswere then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC. The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.
We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.
We developed a process for fabricating nitride superconductor-based superconducting qubits monolithically integrated with a single flux quantum (SFQ)-based readout and control circuits. Since we used a Josephson junction (JJ) made of an NbN/AlN/NbN tri-layer, including a critical current density (Jc) of 50 A/cm2as the suitable material for superconducting qubits and SFQ readout/control circuits operating at 20 mK, the JJs for both the qubits and the SFQ circuits could simultaneously be fabricated. The device structure was also composed of three superconductive layers, comprising two superconductive layers as wiring layers and other layers as the top ground plane. Then, we used a Pd film as the resistive layer, which is required as the shunt resistors and the bias resistors for the SFQ control circuits, followed by an investigation of the properties of NbN/AlN/NbN epitaxial junctions and evaluation of the sheet inductance of the base NbN and wiring NbTiN layer. Our results showed the successful fabrication of a JJ with a sufficiently low leakage current and aJcof around 50 A/cm2, which was close to the target value. Furthermore, the evaluated sheet inductance exceeded 1 pH, which was several times larger than the values obtained for Nb-integrated circuits.
A promising application of a single-flux quantum (SFQ) circuit is read-out circuitry for a multi-channel superconductive sensor array. In such applications, the SFQ read-out circuit is expected to operate outside a magnetic shield. We investigated an SFQ circuit structure, which is tolerant to an external magnetic field, using the AIST 2.5kA/cm2 Nb standard 2 process, which has four Nb wiring layers including the ground plane. By covering the entire circuit using an upper Nb wiring layer called the control (CTL) layer, the influences of the external magnetic field on the SFQ circuit operation can be avoided. We experimentally evaluated the sheet inductance of the wiring layer underneath the CTL shielding layer to design a magnetic-field-tolerant SFQ circuit. We implemented and measured test circuits comprising toggle flip-flops (TFFs) to evaluate their magnetic field tolerances. The operating margin and maximum operating frequency of the designed TFF did not deteriorate with increases in the magnetic field applied to the test circuit, whereas the operating margin of the conventional TFF was reduced by applying the magnetic field. We have also demonstrated the high-speed operation of the designed TFF operated in an unshielded environment at a frequency of up to 120GHz with a wide operating margin.
We report low-power single-flux-quantum (SFQ) circuits fabricated with a lowered critical current density process and low-voltage design. We selected 250 A/cm2^{2}2to obtain 2–10 μA Josephson junctions (JJs) easily using conventional facilities. Our numerical simulation shows that the expected operating frequency is 10 GHz and that we can reduce the bias voltage to 0.1–0.5 mV; power consumption can be reduced to around 1 nW per JJ. We newly developed a fabrication process featuring four planarized Nb layers and a Pd resistor layer. We obtained the correct operation of several basic SFQ circuit elements designed with the lowered critical currents to 1/2 of the conventional circuits at 4.2 K. We also evaluated the Josephson junction critical currents, specific capacitance, resistance, and inductance at 3 K and 300 mK. We observed an increase of 7% in the critical currents at 300 mK, while the other parameters were unchanged. We demonstrated a 0.5-mV Josephson transmission line where we lowered the critical currents to 1/10. We expect such low-power SFQ circuits to operate at 20 mK, providing classical, general-purpose digital processing near quantum bits.
Recent progress in cell-based design (CBD) methods has led to the development of fully operational single-flux-quantum (SFQ) logic circuits including more than 5000 Josephson junctions (JJs). However, there are two problems with this design approach. One is the large cell size, and the other is that it requires the area of the wiring cells to occupy about 80% of the whole circuit area. Because of these problems, the junction density, excluding the junctions used for wiring, is only as high as 30K JJ cm −2 with the current NEC standard process. To improve the integration density, we propose a new design approach based on a multi-wiring-layer process. This approach is simple and quite similar to the gate-array approach used in semiconductor circuit design. The logic cell area in a full adder circuit based on our approach is estimated to be about 68% of the total circuit area, which is drastically better than the value of 20% with conventional CBD. For the current NEC standard process, the circuit density is also improved, to about 0.84M JJ cm −2 with a minimum feature size of 1.5 µm and an alignment margin of 0.5 µm.