Recent progress in cell-based design (CBD) methods has led to the development of fully operational single-flux-quantum (SFQ) logic circuits including more than 5000 Josephson junctions (JJs). However, there are two problems with this design approach. One is the large cell size, and the other is that it requires the area of the wiring cells to occupy about 80% of the whole circuit area. Because of these problems, the junction density, excluding the junctions used for wiring, is only as high as 30K JJ cm −2 with the current NEC standard process. To improve the integration density, we propose a new design approach based on a multi-wiring-layer process. This approach is simple and quite similar to the gate-array approach used in semiconductor circuit design. The logic cell area in a full adder circuit based on our approach is estimated to be about 68% of the total circuit area, which is drastically better than the value of 20% with conventional CBD. For the current NEC standard process, the circuit density is also improved, to about 0.84M JJ cm −2 with a minimum feature size of 1.5 µm and an alignment margin of 0.5 µm.
Recent progress in cell-based design (CBD) methods has led to the development of fully operational single-flux-quantum (SFQ) logic circuits including more than 5000 Josephson junctions (JJs). However, there are two problems with this design approach. One is the large cell size, and the other is that it requires the area of the wiring cells to occupy about 80% of the whole circuit area. Because of these problems, the junction density, excluding the junctions used for wiring, is only as high as 30K JJ cm −2 with the current NEC standard process. To improve the integration density, we propose a new design approach based on a multi-wiring-layer process. This approach is simple and quite similar to the gate-array approach used in semiconductor circuit design. The logic cell area in a full adder circuit based on our approach is estimated to be about 68% of the total circuit area, which is drastically better than the value of 20% with conventional CBD. For the current NEC standard process, the circuit density is also improved, to about 0.84M JJ cm −2 with a minimum feature size of 1.5 µm and an alignment margin of 0.5 µm.
The introduction of passive-transmission-line (PTL) wiring to large-scale SFQ logic circuits offers several advantages over traditional Josephson-transmission-line (JTL) wiring, such as smaller wiring area, less delay, lower power consumption, and more freedom in routing. PTL wiring can drastically change the style of designing SFQ logic circuits. We propose a new methodology for designing large-scale SFQ circuits using PTL wiring. Aiming at generalizing SFQ circuit design, we chose synchronous clocking. We developed a placer that was suitable for SFQ circuit design to assist us with the new design methodology. The placer first synthesizes an H-tree clock distribution network, placing SFQ pulse splitter cells at each branch. It then places logic cells to minimize the maximum length of data PTL wires, aiming at higher operating speeds. Finally, a router completes the PTL wiring. To evaluate the design methodology we designed an 8-bit general purpose RISC processor. Within twelve hours, we obtained a 15-mm-square SFQ circuit that could operate up to 27.6 GHz. We adopted an advanced Nb process, which was characterized by a critical current density of 10 kA/cm2, two 5-mum-wide PTL wiring layers, and a minimum cell size of 30 mum times 30 mum. The circuit consisted of about 20,000 logic cells, which approximated more than 400,000 Josephson junctions including splitters to distribute the clock signal.
The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a Jc = 2.5 kA cm−2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a Jc = 10 kA cm−2, nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a Jc = 40 kA cm−2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.
A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5kA/cm2 to 10kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100GHz.
Abstract We present SIMIT-Nb08, an eight-layer Nb-based fabrication process for double-active-layer single-flux-quantum (SFQ) digital circuits, aimed at overcoming the routing congestion and integration ‘density wall’ of planar SFQ designs. Both Nb/Al–AlO x /Nb JJ layers were designed with the same nominal critical current density of J c = 6 kA cm −2 , and the measured values were 6.15 and 6.26 kA cm −2 for the lower and upper JJ layers, respectively. This architecture incorporates a dual-ground-plane structure to reduce interlayer electromagnetic coupling and shield stray magnetic flux generated by bias lines. A stop-on-metal chemical mechanical polishing module was implemented to provide a controlled dielectric thickness and a planar surface for upper-layer device fabrication. We validate a double-layer SFQ logic cell library with wide DC bias margins on both layers, and demonstrate ultra-high-speed dynamic operation via a toggle flip-flop-based frequency-divider test exceeding 100 GHz. In addition, the process and cross-layer interconnect reliability are demonstrated by functional operation of a cross-layer one-bit full adder and an eight-bit shift register (SR), where the SR exhibits an effective junction-density improvement of ∼4× over typical single-layer implementations. Post-route benchmarking on a 320-cell SR indicates that SIMIT-Nb08 delivers substantial improvements in power, performance, and area, including a 32.2% reduction in area, a 25.0% increase in maximum operating frequency ( f max ), and a 65.3% reduction in estimated power compared with SIMIT-Nb03 (29.9%, 6.3%, and 62.5%, respectively, compared with SIMIT-Nb04), indicating its potential for routing-constrained SFQ digital circuits.
We report low-power single-flux-quantum (SFQ) circuits fabricated with a lowered critical current density process and low-voltage design. We selected 250 A/cm2to obtain 2–10 μA Josephson junctions (JJs) easily using conventional facilities. Our numerical simulation shows that the expected operating frequency is 10 GHz and that we can reduce the bias voltage to 0.1–0.5 mV; power consumption can be reduced to around 1 nW per JJ. We newly developed a fabrication process featuring four planarized Nb layers and a Pd resistor layer. We obtained the correct operation of several basic SFQ circuit elements designed with the lowered critical currents to 1/2 of the conventional circuits at 4.2 K. We also evaluated the Josephson junction critical currents, specific capacitance, resistance, and inductance at 3 K and 300 mK. We observed an increase of 7% in the critical currents at 300 mK, while the other parameters were unchanged. We demonstrated a 0.5-mV Josephson transmission line where we lowered the critical currents to 1/10. We expect such low-power SFQ circuits to operate at 20 mK, providing classical, general-purpose digital processing near quantum bits.
We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (IC), bias current (Ibias), and inductance satisfied minimal margin requirements. Critical margins of ICand Ibiaswere then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC. The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.