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IEEE Transactions on Applied Superconductivity

Submicrometer ${\rm Nb}/{\rm Al}{-}{\rm AlO}_{\rm x}/{\rm Nb}$ Integrated Circuit Fabrication Process for Quantum Computing Applications

Bruce Bumble, A. Fung, Anupama B. Kaul, Alan W. Kleinsasser, G.L. Kerber, P. Bunyk, E. Ladizinsky

Published Jun 1, 2009• 13 citations
Publisher

Abstract

We have developed a low Jc(100-1000 A/cm2) submicrometer Nb integrated circuit fabrication process for SQUID-based quantum computing applications. The baseline process consists of 7 masking steps including Pd-Au resistor, Nb/Al-AlOx/Nb trilayer, two Nb wiring layers and two sputtered SiO2dielectric layers. We have also fabricated wafers with an Nb ground plane. Using deep-UV lithography, inductively coupled plasma etch tools, and self-aligned lift-off for device definition, we routinely achieve micrometer lines and spaces with 400 nm minimum junction dimensions. Room temperature testing is used to select wafers in process and junction annealing has been calibrated for trimming current density. We will describe the process which has been used to produce circuits with over 100 junctions.

DOI
10.1109/tasc.2009.2018249

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Submicrometer Nb/Al−AlOx/Nb{\rm Nb}/{\rm Al}{-}{\rm AlO}_{\rm x}/{\rm Nb}Nb/Al−AlOx​/Nb Integrated Circuit Fabrication Process for Quantum Computing Applications
We have developed a low Jc(100-1000 A/cm2) submicrometer Nb integrated circuit fabrication process for SQUID-based quantum computing applications. The baseline process consists of 7 masking steps including Pd-Au resistor, Nb/Al-AlOx/Nb trilayer, two Nb wiring layers and two sputtered SiO2dielectric layers. We have also fabricated wafers with an Nb ground plane. Using deep-UV lithography, inductively coupled plasma etch tools, and self-aligned lift-off for device definition, we routinely achieve micrometer lines and spaces with 400 nm minimum junction dimensions. Room temperature testing is used to select wafers in process and junction annealing has been calibrated for trimming current density. We will describe the process which has been used to produce circuits with over 100 junctions.
We present the latest development of an Nb/Al-AlOx/Nb Josephson junction fabrication process for superconducting integrated circuits at SIMIT. Our fabrication process has four niobium superconducting layers and one Ti/Pd resistor layer with 1.0 Ω/square sheet resistor for junction shunting and circuit biasing. Critical current density Jcof the junctions is controlled from 30 A/cm2to 10 kA/cm2by exposing aluminum layer to pure or mixed O2atmosphere. Correlation between measured Jcand exposure conditions has been established. Average quality factor (Rsg/Rn) of the junctions in our process is larger than 20 with subgap leakage factor (Vm) beyond 30 mV. Critical current uniformity is obtained according to the switching current (Is) distribution of a 1000-JJ array. Measured standard deviation sigma of Isis less than 4% over the 100-mm wafer. Plasma resonance in a large Josephson junction is used to measure specific capacitance (Cs) of the junction. Sheet inductances of superconducting niobium strip-lines are extracted by a SQUID diagnose circuit and the measured results show good agreement with our design values.
We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistanceRshof 2 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction. The target critical current densityJcwas set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.
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To implement a large-scale integration of superconducting quantum bits (qubits), we have investigated a process of fabricating submicrometer Al/AlOx/Al trilayer Josephson junctions. Moreover, on the basis of this process, we developed a means of fabricating different kinds of superconducting qubits. Superconducting qubits require not only small junctions, but also peripheral circuit elements, such as a large resonator, on the same chip. As a result, we chose to use planarization in the self-aligned junction contact formation, which suppressed a pattern-area-dependence of the chemical-mechanical polishing rate. In addition, Al fine wires with a width of 0.2 μm were required in some parts of the qubits to increase the coupling strength between the SQUIDs and qubits. We developed a two-step etching process to form such fine wires using i-line photoresist, which had a high etching resistance. The operation of three-junction flux qubits was confirmed in a dilution refrigerator.
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We have developed our next generation Nb integrated circuit process which offers higher performance, particularly for SFQ-type logic, and increased density compared to our present 2000 A/cm/sup 2/ foundry process. The new process is based on our existing Nb foundry process, but has been optimized to utilize more of the sub-micron alignment and exposure capabilities of our optical lithography tools. Minimum linepitch and junction size have been reduced to 2.5 /spl mu/m (from 4 /spl mu/m) and 1.75 /spl mu/m (from 2.5 /spl mu/m), respectively, and J/sub c/ has been increased to 4000 A/cm/sup 2/. These goals have been achieved by an overall reduction in layer thicknesses, implementation of SF/sub 6/ dry etch for metal line definition, and optimization of the photolithography process. The new process offers lower inductance wiring and substantially lower parasitic circuit inductances compared with the existing Nb foundry process. In this paper, we discuss these improvements and report parametric test data for devices fabricated in this process.