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IEEE Transactions on Applied Superconductivity

Next generation Nb superconductor integrated circuit process

L.A. Abelson, Raffi Elmadjian, G.L. Kerber

Published Jun 1, 1999• 14 citations
Publisher

Abstract

We have developed our next generation Nb integrated circuit process which offers higher performance, particularly for SFQ-type logic, and increased density compared to our present 2000 A/cm/sup 2/ foundry process. The new process is based on our existing Nb foundry process, but has been optimized to utilize more of the sub-micron alignment and exposure capabilities of our optical lithography tools. Minimum linepitch and junction size have been reduced to 2.5 /spl mu/m (from 4 /spl mu/m) and 1.75 /spl mu/m (from 2.5 /spl mu/m), respectively, and J/sub c/ has been increased to 4000 A/cm/sup 2/. These goals have been achieved by an overall reduction in layer thicknesses, implementation of SF/sub 6/ dry etch for metal line definition, and optimization of the photolithography process. The new process offers lower inductance wiring and substantially lower parasitic circuit inductances compared with the existing Nb foundry process. In this paper, we discuss these improvements and report parametric test data for devices fabricated in this process.

DOI
10.1109/77.783716

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We have developed our next generation Nb integrated circuit process which offers higher performance, particularly for SFQ-type logic, and increased density compared to our present 2000 A/cm/sup 2/ foundry process. The new process is based on our existing Nb foundry process, but has been optimized to utilize more of the sub-micron alignment and exposure capabilities of our optical lithography tools. Minimum linepitch and junction size have been reduced to 2.5 /spl mu/m (from 4 /spl mu/m) and 1.75 /spl mu/m (from 2.5 /spl mu/m), respectively, and J/sub c/ has been increased to 4000 A/cm/sup 2/. These goals have been achieved by an overall reduction in layer thicknesses, implementation of SF/sub 6/ dry etch for metal line definition, and optimization of the photolithography process. The new process offers lower inductance wiring and substantially lower parasitic circuit inductances compared with the existing Nb foundry process. In this paper, we discuss these improvements and report parametric test data for devices fabricated in this process.
We report on the development of a 10 K, NbN superconductive integrated circuit (IC) technology that utilizes an improved SiO/sub 2/ interlevel dielectric (ILD) deposition process and a thick NbN ground plane layer to reduce parasitic circuit inductances. The ILD process uses a novel low frequency (40 kHz) substrate bias during sputter deposition of SiO/sub 2/, which produces very smooth oxide films having a roughness less than 0.1 nm (rms) as measured by atomic force microscopy (AFM). Bias-sputtered SiO/sub 2/ is used to planarize and to smooth the surface of the NbN ground plane layer in preparation for fabrication of NbN/MgO/NbN tunnel junctions. High current density tunnel junctions ranging from 1000 A/cm/sup 2/ to 5000 A/cm/sup 2/, fabricated over NbN ground planes up to 1 /spl mu/m thick, exhibit low subgap leakage (V/sub m//spl sim/15 mV at 10 K) and high subgap voltage (V/sub g/=4.4 mV at 10 K). Typical wiring inductance over ground plane has been reduced by 25% compared to our present NbN foundry process.
The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a Jc = 2.5 kA cm−2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a Jc = 10 kA cm−2, nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a Jc = 40 kA cm−2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.
The SNS (Nb/HfTi/Nb) ramp junction technology process has been improved for digital superconducting circuit operation. DC interferometers were realized on an isolated superconducting ground plane, connections being realized through windows in the insulation layers. The inductances of superconducting Nb striplines (widths w down to the sub-/spl mu/m range) were measured. For a 250 nm SiO/sub 2//Nb-oxide insulation layer, the sheet inductances of striplines were determined at 0.382 /spl plusmn/ 0.009, 0.340 /spl plusmn/ 0.005, and 0.293 /spl plusmn/ 0.008 pH (stripline widths: 1.5, 1.0, 0.54 /spl mu/m) and compared with data calculated by different inductance evaluation programs. The Josephson junctions used in the interferometers exhibit a critical current density of j/sub C/=525 kA/cm/sup 2/ and a characteristic voltage of V/sub C/=95 /spl mu/V. The design of an RSFQ converter circuit was developed on the basis of SNS ramp junction technology. For circuit applications the critical current density j/sub C/ was set to 150 kA/cm/sup 2/.
Photosensitive polyimide insulation layers have been introduced to fabricate superconducting integrated circuits. It is shown to simplify the fabrication process, because the photosensitive polyimide insulation layer can be patterned by conventional photolithography process, resulting in the etching process unnecessary in the present new fabrication process. Three kinds of contact hole (junction top electrode contact, junction base electrode contact, and resistor contact) are simultaneously formed in the photolithography process of the polyimide. A minimum contact hole size is designed to be 1.5 /spl mu/m square for a 3 /spl mu/m /spl times/ 3 /spl mu/m squared junction. Superconducting current density of 2.4/spl times/10/sup 6/ A/cm/sup 2/ of the contact hole was measured. Palladium resistors were successfully made with through hole contacts of the photosensitive polyimide insulation layer. We demonstrated superconducting integrated circuits using this new fabrication process including the minimum 3 /spl mu/m /spl times/ 3 /spl mu/m squared Nb/Al-AlO/sub x//Nb Josephson tunnel junction. The circuit operation is also demonstrated in the fabricated superconducting integrated circuits with the photosensitive polyimide insulation layers.
In NEC's standard process, the minimum junction size is 2 µm and the critical current density ( J C ) is 2.5 kA cm -2 . In the process, i-line stepper lithography and reactive ion etching with SF 6 gas are used and the standard deviation ( ) of the critical current ( I C ) was 0.9% for the 2 µm junctions. This junction uniformity enables integration of more than 10M junctions if an I C variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits.
Submicrometer Nb/Al−AlOx/Nb{\rm Nb}/{\rm Al}{-}{\rm AlO}_{\rm x}/{\rm Nb}Nb/Al−AlOx​/Nb Integrated Circuit Fabrication Process for Quantum Computing Applications
We have developed a low Jc(100-1000 A/cm2) submicrometer Nb integrated circuit fabrication process for SQUID-based quantum computing applications. The baseline process consists of 7 masking steps including Pd-Au resistor, Nb/Al-AlOx/Nb trilayer, two Nb wiring layers and two sputtered SiO2dielectric layers. We have also fabricated wafers with an Nb ground plane. Using deep-UV lithography, inductively coupled plasma etch tools, and self-aligned lift-off for device definition, we routinely achieve micrometer lines and spaces with 400 nm minimum junction dimensions. Room temperature testing is used to select wafers in process and junction annealing has been calibrated for trimming current density. We will describe the process which has been used to produce circuits with over 100 junctions.