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IEEE Transactions on Applied Superconductivity

Efficient Fabrication Process for Superconducting Integrated Circuits Using Photosensitive Polyimide Insulation Layers

Katsuya Kikuchi, M. Goto, Hiroshi Nakagawa, Shigemasa Segawa, Kazuhiko Tokoro, Tohru Taino, Hiroaki Myoren, S. Takada, Masahiro Aoyagi

Published Jun 1, 2005• 6 citations
Publisher

Abstract

Photosensitive polyimide insulation layers have been introduced to fabricate superconducting integrated circuits. It is shown to simplify the fabrication process, because the photosensitive polyimide insulation layer can be patterned by conventional photolithography process, resulting in the etching process unnecessary in the present new fabrication process. Three kinds of contact hole (junction top electrode contact, junction base electrode contact, and resistor contact) are simultaneously formed in the photolithography process of the polyimide. A minimum contact hole size is designed to be 1.5 /spl mu/m square for a 3 /spl mu/m /spl times/ 3 /spl mu/m squared junction. Superconducting current density of 2.4/spl times/10/sup 6/ A/cm/sup 2/ of the contact hole was measured. Palladium resistors were successfully made with through hole contacts of the photosensitive polyimide insulation layer. We demonstrated superconducting integrated circuits using this new fabrication process including the minimum 3 /spl mu/m /spl times/ 3 /spl mu/m squared Nb/Al-AlO/sub x//Nb Josephson tunnel junction. The circuit operation is also demonstrated in the fabricated superconducting integrated circuits with the photosensitive polyimide insulation layers.

DOI
10.1109/tasc.2005.849702

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Photosensitive polyimide insulation layers have been introduced to fabricate superconducting integrated circuits. It is shown to simplify the fabrication process, because the photosensitive polyimide insulation layer can be patterned by conventional photolithography process, resulting in the etching process unnecessary in the present new fabrication process. Three kinds of contact hole (junction top electrode contact, junction base electrode contact, and resistor contact) are simultaneously formed in the photolithography process of the polyimide. A minimum contact hole size is designed to be 1.5 /spl mu/m square for a 3 /spl mu/m /spl times/ 3 /spl mu/m squared junction. Superconducting current density of 2.4/spl times/10/sup 6/ A/cm/sup 2/ of the contact hole was measured. Palladium resistors were successfully made with through hole contacts of the photosensitive polyimide insulation layer. We demonstrated superconducting integrated circuits using this new fabrication process including the minimum 3 /spl mu/m /spl times/ 3 /spl mu/m squared Nb/Al-AlO/sub x//Nb Josephson tunnel junction. The circuit operation is also demonstrated in the fabricated superconducting integrated circuits with the photosensitive polyimide insulation layers.
We propose a new fabrication process for Superconducting Quantum Interference Devices (SQUIDs) with Nb/Al/AlOx/Nb junctions by using photosensitive polyimide insulation layers. The photosensitive polyimide, which is synthesized by multi-block copolymerization, can be formed into a thin layer with spin-coating, and patterned with conventional photolithography. Compared to forming a SiO/sub 2/ insulation layer with a sputtering and etching process, the fabrication is simplified and the coverage over the edge of the patterns can be improved due to planarization. SQUIDs with a flux transformer having two insulation layers were successfully fabricated with this process and were characterized. The critical current of the flux transformer was more than 20 mA, and a flux noise of less than 1/spl times/10/sup -6/ /spl Phi//sub 0///spl radic/Hz was obtained in the white region. With an axial gradiometer in combination with this SQUID, a field resolution of 1.5 fT//spl radic/Hz was achieved.
We have developed our next generation Nb integrated circuit process which offers higher performance, particularly for SFQ-type logic, and increased density compared to our present 2000 A/cm/sup 2/ foundry process. The new process is based on our existing Nb foundry process, but has been optimized to utilize more of the sub-micron alignment and exposure capabilities of our optical lithography tools. Minimum linepitch and junction size have been reduced to 2.5 /spl mu/m (from 4 /spl mu/m) and 1.75 /spl mu/m (from 2.5 /spl mu/m), respectively, and J/sub c/ has been increased to 4000 A/cm/sup 2/. These goals have been achieved by an overall reduction in layer thicknesses, implementation of SF/sub 6/ dry etch for metal line definition, and optimization of the photolithography process. The new process offers lower inductance wiring and substantially lower parasitic circuit inductances compared with the existing Nb foundry process. In this paper, we discuss these improvements and report parametric test data for devices fabricated in this process.
Development of 15kA/cm2^22 Fabrication Process for Superconducting Integrated Digital Circuits
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 ΩΩΩ, followed by the deposition of Nb/Al-AlOx_xx​/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm2^22. To increase the Al-AlOx_xx​ barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.
To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.
For enhancing operating speed of a superconducting integrated circuit (IC), the device size must be reduced into the submicron level. For this purpose, we have introduced electron beam (EB) direct writing technique into the fabrication process of a Nb/AlOx/Nb Josephson IC. A two-layer (PMMA/(alpha) M-CMS) resist method called the portable conformable mask (PCM) method was utilized for having a high aspect ratio. The electron cyclotron resonance (ECR) plasma etching technique was utilized. We have fabricated micron or submicron-size Nb/AlOx/Nb Josephson junctions, where the size of the junction was varied from 2 micrometer to 0.5 micrometer at 0.1 micrometer intervals. These junctions were designed for evaluating the spread of the junction critical current. We achieved minimum-to-maximum Ic spread of plus or minus 13% for 0.81-micrometer-square (plus or minus 16% for 0.67-micrometer-square) 100 junctions spreading in 130- micrometer-square area. The size deviation of 0.05 micrometer was estimated from the spread values. We have successfully demonstrated a small-scale logic IC with 0.9-micrometer-square junctions having a 50 4JL OR-gate chain, where 4JL means four junctions logic family. The circuit was designed for measuring the gate delay. We obtained a preliminary result of the OR- gate logic delay, where the minimum delay was 8.6 ps/gate.
A multilevel thin-film process has been developed for fabricating experimental circuits containing Josephson tunneling gates, insulated crossings, superconducting contacts, and terminating resistors. The process utilizes a Nb film for the ground plane and Pb alloy films for overlying superconducting layers. Insulation is achieved through the use of vacuum-deposited SiO films and anodization of the Nb ground plane. An oxide formed by rf sputter-etching in an oxygen plasma is used for forming the tunneling barriers. Photoprocessing techniques are used for patterning. Through use of the process it has been possible to fabricate experimental memory and logic circuits which survive thermal cycling to 4.2 K and intervening storage at room temperature without significant changes in electrical characteristics.