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IEEE Transactions on Applied Superconductivity

An improved NbN integrated circuit process featuring thick NbN ground plane and lower parasitic circuit inductances

G.L. Kerber, L.A. Abelson, Raffi Elmadjian, G. Hanaya, E. Ladizinsky

Published Jun 1, 1997• 35 citations
Publisher

Abstract

We report on the development of a 10 K, NbN superconductive integrated circuit (IC) technology that utilizes an improved SiO/sub 2/ interlevel dielectric (ILD) deposition process and a thick NbN ground plane layer to reduce parasitic circuit inductances. The ILD process uses a novel low frequency (40 kHz) substrate bias during sputter deposition of SiO/sub 2/, which produces very smooth oxide films having a roughness less than 0.1 nm (rms) as measured by atomic force microscopy (AFM). Bias-sputtered SiO/sub 2/ is used to planarize and to smooth the surface of the NbN ground plane layer in preparation for fabrication of NbN/MgO/NbN tunnel junctions. High current density tunnel junctions ranging from 1000 A/cm/sup 2/ to 5000 A/cm/sup 2/, fabricated over NbN ground planes up to 1 /spl mu/m thick, exhibit low subgap leakage (V/sub m//spl sim/15 mV at 10 K) and high subgap voltage (V/sub g/=4.4 mV at 10 K). Typical wiring inductance over ground plane has been reduced by 25% compared to our present NbN foundry process.

DOI
10.1109/77.621781

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We report on the development of a 10 K, NbN superconductive integrated circuit (IC) technology that utilizes an improved SiO/sub 2/ interlevel dielectric (ILD) deposition process and a thick NbN ground plane layer to reduce parasitic circuit inductances. The ILD process uses a novel low frequency (40 kHz) substrate bias during sputter deposition of SiO/sub 2/, which produces very smooth oxide films having a roughness less than 0.1 nm (rms) as measured by atomic force microscopy (AFM). Bias-sputtered SiO/sub 2/ is used to planarize and to smooth the surface of the NbN ground plane layer in preparation for fabrication of NbN/MgO/NbN tunnel junctions. High current density tunnel junctions ranging from 1000 A/cm/sup 2/ to 5000 A/cm/sup 2/, fabricated over NbN ground planes up to 1 /spl mu/m thick, exhibit low subgap leakage (V/sub m//spl sim/15 mV at 10 K) and high subgap voltage (V/sub g/=4.4 mV at 10 K). Typical wiring inductance over ground plane has been reduced by 25% compared to our present NbN foundry process.
A new NbN multilayer technology has been developed on 3 inch diameter R-plane sapphire substrates, for combining on-chip fast RSFQ circuits with GHz bandwidth optical links, The circuits take advantage of two high quality [110] NbN layers sputtered epitaxially on sapphire at 600/spl deg/C and selectively patterned: a 400 nm thick layer (/spl lambda//sub L//spl sim/250 nm at 6 K) acts for the ground-plane and microbridge photodetectors are made of a 3.5-8 nm thick NbN epilayer with T/sub c/ above 11 K. Innovative dielectrics formed of 10 nm thick MgO sputtered on top of 200 mm SiO/sub 2/ layers are found to improve significantly the superconductivity of NbN junction electrode lines deposited below 300/spl deg/C. Good quality, hysteretic 2 /spl mu/m/sup 2/ area, NbN/MgO/NbN junctions with high J/sub c/ (up to 50 kA/cm/sup 2/) are obtained with very large gap voltage (6.20 mV) and low sub-gap leakage current (V/sub m/>15 mV) at 4.2 K. At 11 K such junctions are found self-shunted (J/sub c//spl sim/10 k4/cm/sup 2/) with R/sub n/I/sub c/ above 0.5 mV and with low J/sub c/ spread in arrays. J/sub c/ can be adjusted (reduced) without any detrimental effect on the junction quality or spread by annealing at 250/spl deg/C.
A generic NbN Superconducting Tunnel Junctions (STJ) technology has been developed using conventional substrates (Si and SOI-SIMOX) for making THz spectrometers including SIS receivers and RSFQ logic gates. NbN/MgO/NbN junctions with area of 1 /spl mu/m/sup 2/, Jc of 10 kA/cm/sup 2/ and low sub-gap leakage current (Vm>25 mV) are currently obtained from room temperature sputtered multilayers followed by a post-annealing at 250/spl deg/C. Using a thin MgO buffer layer deposited underneath the NbN electrodes, ensures lower NbN surface resistance values (Rs=7 /spl mu//spl Omega/) at 10 GHz and 4 K. Epitaxial NbN [100] films on MgO [100] with high gap frequency (1.4 THz) have also been achieved under the same deposition conditions at room temperature. The NbN SIS has shown good I-V photon induced steps when LO pumped at 300 GHz. We have developed an 8 levels Al/NbN multilayer process for making 1.5 THz SIS mixers (including Al antennas) on Si membranes patterned in SOI-SIMOX. Using the planarization techniques developed at the Si-MOS CEA-LETI Facility, we have also demonstrated on the possibility of extending our NbN technology to high level RSFQ circuit integration with 0.5 /spl mu/m/sup 2/ junction area, made on large area substrates (up to 8 inches).
We have developed our next generation Nb integrated circuit process which offers higher performance, particularly for SFQ-type logic, and increased density compared to our present 2000 A/cm/sup 2/ foundry process. The new process is based on our existing Nb foundry process, but has been optimized to utilize more of the sub-micron alignment and exposure capabilities of our optical lithography tools. Minimum linepitch and junction size have been reduced to 2.5 /spl mu/m (from 4 /spl mu/m) and 1.75 /spl mu/m (from 2.5 /spl mu/m), respectively, and J/sub c/ has been increased to 4000 A/cm/sup 2/. These goals have been achieved by an overall reduction in layer thicknesses, implementation of SF/sub 6/ dry etch for metal line definition, and optimization of the photolithography process. The new process offers lower inductance wiring and substantially lower parasitic circuit inductances compared with the existing Nb foundry process. In this paper, we discuss these improvements and report parametric test data for devices fabricated in this process.
We report on the fabrication and the operation of all-NbN rapid single flux quantum (RSFQ) circuits. The NbN integrated circuit consists of NbN/AlN/NbN tunnel junctions, Mo resistors, sputtered SiO/sub 2/ insulating layers, and 400-nm-thick NbN ground plane and wiring layer. The circuits were fabricated with the minimum junction size of 2 /spl mu/m/spl times/2 /spl mu/m and the alignment margin of +/-0.5 /spl mu/m. We designed RSFQ logic cells under critical current density of 2.5 kA/cm/sup 2/, sheet resistance of 2 /spl Omega/ and sheet inductance of 1.4 pH. We experimentally investigated dc bias margin of the fabricated RSFQ cells at 9 K. We observed relatively large dc bias margin of more than +/-25% for a pulse splitter, a confluence buffer and an RS flip-flop, while the dc bias margin of a T flip-flop was less than +/-5%. We succeeded to demonstrate the operation of 16-bit concurrent flow shift register at 9 K.
We have evaluated the electrical characteristics of NbN/Al-AlNx/NbN tunnel junctions fabricated on sapphire-C or fused-silica substrates. NbN/Al-AlNx/NbN multilayers were prepared by reactive dc-magnetron sputtering deposition of lower and upper NbN layers, and rf-magnetron sputtering deposition of the Al layer, followed by radical-nitridation. The junctions showed low sub-gap leakage currents in the current-voltage characteristics at 4.2 K. The quality parameter, Rsg/Rn, where respective Rsgand Rnare the sub-gap resistance at 2 mV and junction resistance at 5 mV, was above 15. The gap voltage (Vg) was around 3.3 mV, which was reduced in comparison with Vgvalues of ~4.3 mV for junctions on MgO substrates. The reduced Vgwas caused by superconducting properties of lower NbN layers deposited on the sapphire or fused-silica substrates. Uniformity in critical current (Ic) was relatively good, and the maximum-to-minimum spread in Icwas ±1.7% for 200 junctions on a sapphire substrate and ±2.0% for the junctions on a fused-silica substrate.
NbN-TaN-Nb(Ti)N non-hysteretic SNS Josephson junctions with TaXN barriers tuned through nitrogen content at metal-insulator transition have been produced in a reliable way with characteristic voltage RNICabove 1.5 mV at 9 K. Barriers are typically 7-10 nm thick and Jc in the range 5 to 25 kA/cm-2making feasible LSI RSFQ ADC circuit integration by using the lithographic tools of the Leti C-MOS platform. Junction tri-layers, NbTiN ground-plane and wiring levels have been reactively sputtered and optimized at 300°C in a reproducible way on 8-inch oxidized silicon wafers. A deep UV stepper combined with SF6 gas mixtures RIE has been used to achieve low spread lithography in junction diameters of 716 nm (3σ ~ 40 nm), of 465 nm (3σ ~ 84 nm) across the 8-inch. A well controlled CMP planarization process has been developed on thick PE-CVD silica layers deposited on each superconducting nitride layer. On-line FIB-SEM observations and electrical characterizations associated to the development of a technology test vehicle demonstrate the feasibility of the complete process. The reliable production of nitrides LSI RSFQ circuits such as ADCs and integrated imagers operating in a relaxed cryogenic environment in the 6-10 K temperature range is foreseen to open new telecoms and medical applications. Moreover, a new MgO-AlN-MgO layered insulating barrier junction is shown to operate above 10 K and will be developed for analog front-end circuit parts.