We present a fabrication technology for nanoscale superconducting quantum interference devices (SQUIDs) with overdamped superconductor-normal metal-superconductor (SNS) trilayer Nb/HfTi/Nb Josephson junctions. A combination of electron-beam lithography with chemical-mechanical polishing and magnetron sputtering on thermally oxidized Si wafers is used to produce direct current SQUIDs with 100-nm-lateral dimensions for Nb lines and junctions. We extended the process from originally two to three independent Nb layers. This extension offers the possibility to realize superconducting vias to all Nb layers without the HfTi barrier, and hence to increase the density and complexity of circuit structures. We present results on the yield of this process and measurements of SQUID characteristics.
We present a fabrication technology for nanoscale superconducting quantum interference devices (SQUIDs) with overdamped superconductor-normal metal-superconductor (SNS) trilayer Nb/HfTi/Nb Josephson junctions. A combination of electron-beam lithography with chemical-mechanical polishing and magnetron sputtering on thermally oxidized Si wafers is used to produce direct current SQUIDs with 100-nm-lateral dimensions for Nb lines and junctions. We extended the process from originally two to three independent Nb layers. This extension offers the possibility to realize superconducting vias to all Nb layers without the HfTi barrier, and hence to increase the density and complexity of circuit structures. We present results on the yield of this process and measurements of SQUID characteristics.
Abstract Josephson tunnel junctions form the basis for various superconductor electronic devices. For this reason, enormous efforts are routinely taken to establish and later on maintain a scalable and reproducible wafer-scale manufacturing process for high-quality Josephson junctions. Here, we present an anodization-free fabrication process for Nb/Al-AlO x /Nb cross-type Josephson junctions that requires only a small number of process steps and that is in general intrinsically compatible with wafer-scale fabrication. We show that the fabricated junctions are of very high quality and, compared to other junction types, exhibit not only a significantly reduced capacitance but also an almost rectangular critical current density profile. Our process hence enables the usage of low capacitance Josephson junctions for superconductor electronic devices such as ultra-low noise dc-superconducting quantum interference devices (SQUIDs), microwave SQUID multiplexers based on non-hysteretic rf-SQUIDs and RFSQ circuits.
We analyze electric transport and noise properties at 4.2 K of self-shunted superconductor-normal metal-superconductor (SNS) sandwich-type Josephson junctions, comprising Nb as the superconductor and Hf-Ti as the normal conducting material, with lateral dimensions down to approximately 80 nm. The junctions are fabricated with an optimized multilayer Nb technology based on nanopatterning by electron-beam lithography and chemical-mechanical polishing. The dependence of transport properties on the junction geometry (lateral size and barrier thickness ${d}_{\mathrm{Hf}\mathrm{\ensuremath{-}}\mathrm{Ti}}$) is studied, yielding a characteristic voltage Vc up to approximately $100\phantom{\rule{0.2em}{0ex}}\ensuremath{\mu}\mathrm{V}$ for the smallest ${d}_{\mathrm{Hf}\mathrm{\ensuremath{-}}\mathrm{Ti}}=17$ nm. The observed small hysteresis in the current-voltage curves of devices with high Vc and large size can be attributed to self-heating of the junctions and fitted with an extended version of the resistively shunted junction model. Measurements of voltage noise of single junctions are consistent with the model including self-heating effects. The potential of our technology for further miniaturization of nanoscale superconducting quantum interference devices and for the improvement of their performance is discussed.
We present the fabrication of nanoscale superconducting quantum interference devices (SQUIDs) at the apex of wireframe tips on self-aligned superconducting cantilever probes. The probes are made on silicon wafers using molding techniques in combination with corner lithography, which results in a nanowire frame tip with a tunable apex structure. A shadow-effect deposition using magnetron sputtering of niobium creates self-aligned superconducting wireframes on cantilevers with accompanying device circuitry. Superconducting weak links are realized at the apex of the wireframes with the use of focused ion beam nanopatterning. The realized SQUIDs have effective diameters ranging from several micrometers down to 100 nm and can be operated in magnetic fields up to 1 T. Furthermore, the nanowires in the wireframe can be used to flux modulate the SQUID locally. This fabrication process enables the production of wafer-scale templates for probes based on on-tip superconducting devices.
Abstract Superconducting flux memory devices fabricated with nanoscale junctions and high-inductance materials can maintain high-speed access performance while significantly reducing the area required for superconducting loops. In this work, we present a method for preparing nanoscale NbN-based superconductor/normal-metal/superconductor (SNS) Josephson junctions that combines electron beam lithography with chemical mechanical planarization process. Scanning electron microscope images reveal that the junction has a very round shape, while cross-sectional transmission electron microscopy shows that it has a truncated cone structure, characterized by a narrow top and a wide bottom. The minimum diameter of the junction is 51 nm, with the diameter at the interface between the wiring layer and the top electrode being just 27 nm. These nanoscale junctions exhibit excellent Josephson properties with a critical current density J c of 673 ± 64 kA cm −2 and a characteristic voltage V c of 1.63 ± 0.45 mV at 4.2 K. Furthermore, we designed the superconducting memory cell based on the simulated inductance values of the NbN loop and the nanoscale NbN-based SNS junctions. The cell has a total area of 12.6 μ m × 6.5 μ m and contains a radio-frequency superconducting quantum interference device with one junction in the storage loop and a direct-current superconducting quantum interference device with two junctions in the readout loop. Using the flux-locked and feedback measurement method, a clear flux hysteresis curve can be obtained to verify the read-write functions of the device.
Abstract The progressive miniaturization of superconducting quantum interference devices (SQUIDs) used, e.g. for magnetic imaging on the nanoscale or for the detection of the magnetic states of individual magnetic nanoparticles causes increasing problems in realizing a proper flux-bias scheme for reading out the device. To overcome the problem, a multi-terminal, multi-junction layout has been proposed and realized recently for the SQUID-on-tip configuration, which uses constriction-type Josephson junctions (JJ). This geometry is also interesting for SQUIDs based on overdamped superconductor—normal metal—superconductor (SNS) JJ. We fabricated four-terminal, four-junction SQUIDs based on a trilayer Nb/HfTi/Nb process and study their static and dynamic transport properties in close comparison with numerical simulations based on the resistively and capacitively shunted junction model. Simulations and measurements are in very good agreement. However, there are large differences to the transport properties of conventional two-junction SQUIDs, including unusual phase-locked and chaotic dynamic states which we describe in detail. We further extract the current-phase relation of our SNS junctions, which turns out to be purely sinusoidal within the experimental error bars.
Planarized Process for Single-Flux-Quantum Circuits With Self-Shunted Nb/NbxSi1−x/Nb Josephson Junctions
We describe our process for fabricating single-flux-quantum circuits for applications in communications metrology, advanced computing, and quantum information. The process flow includes four superconducting metal layers, one junction layer, one palladium-gold bias resistor layer, and a contact pad layer. Planarization using chemical-mechanical polishing is performed on the two lower insulating layers. This process is based on Josephson junctions with niobium superconducting electrodes and self-shunted, amorphous niobium-doped silicon barriers on the insulating side near the metal-insulator transition. The barrier material is deposited by cosputtering silicon and niobium, with the junction properties controlled by the relative sputtering powers and the duration of the barrier deposition step. The profiles of the deposition rates across 3-in (76.2 mm) wafers give a corresponding radial profile of the critical current density Jcthat increases by ~46% from the center to the edge of the wafer. To characterize our process, we have measured and show data for niobium metal quality and its magnetic penetration depth, as well as for wire and via inductances, and for via critical currents. The uniformity of the junction critical current Icacross a wafer was measured on test chips with 2.7-μm-diameter junctions. Within a 5 mm × 5 mm area, the standard deviation of Icwas ~2% for chips near the center of the wafer and up to ~7% for chips near the edge. We also describe process improvements and innovations under development aimed at increasing circuit density and high-speed performance.