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IEEE Transactions on Applied Superconductivity

Planarized Process for Single-Flux-Quantum Circuits With Self-Shunted Nb/Nb$_{x}$Si$_{1-x}$/Nb Josephson Junctions

David I. Olaya, Manuel A. Castellanos-Beltran, Javier F. Pulecio, John Biesecker, Soroush Khadem, Lewitt Theodore, P. F. Hopkins, Paul D. Dresselhaus, Samuel P. Benz

Published Mar 16, 2019• 26 citations
Publisher

Abstract

We describe our process for fabricating single-flux-quantum circuits for applications in communications metrology, advanced computing, and quantum information. The process flow includes four superconducting metal layers, one junction layer, one palladium-gold bias resistor layer, and a contact pad layer. Planarization using chemical-mechanical polishing is performed on the two lower insulating layers. This process is based on Josephson junctions with niobium superconducting electrodes and self-shunted, amorphous niobium-doped silicon barriers on the insulating side near the metal-insulator transition. The barrier material is deposited by cosputtering silicon and niobium, with the junction properties controlled by the relative sputtering powers and the duration of the barrier deposition step. The profiles of the deposition rates across 3-in (76.2 mm) wafers give a corresponding radial profile of the critical current density Jcthat increases by ~46% from the center to the edge of the wafer. To characterize our process, we have measured and show data for niobium metal quality and its magnetic penetration depth, as well as for wire and via inductances, and for via critical currents. The uniformity of the junction critical current Icacross a wafer was measured on test chips with 2.7-μm-diameter junctions. Within a 5 mm × 5 mm area, the standard deviation of Icwas ~2% for chips near the center of the wafer and up to ~7% for chips near the edge. We also describe process improvements and innovations under development aimed at increasing circuit density and high-speed performance.

DOI
10.1109/tasc.2019.2900020

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Planarized Process for Single-Flux-Quantum Circuits With Self-Shunted Nb/Nbx_{x}x​Si1−x_{1-x}1−x​/Nb Josephson Junctions
We describe our process for fabricating single-flux-quantum circuits for applications in communications metrology, advanced computing, and quantum information. The process flow includes four superconducting metal layers, one junction layer, one palladium-gold bias resistor layer, and a contact pad layer. Planarization using chemical-mechanical polishing is performed on the two lower insulating layers. This process is based on Josephson junctions with niobium superconducting electrodes and self-shunted, amorphous niobium-doped silicon barriers on the insulating side near the metal-insulator transition. The barrier material is deposited by cosputtering silicon and niobium, with the junction properties controlled by the relative sputtering powers and the duration of the barrier deposition step. The profiles of the deposition rates across 3-in (76.2 mm) wafers give a corresponding radial profile of the critical current density Jcthat increases by ~46% from the center to the edge of the wafer. To characterize our process, we have measured and show data for niobium metal quality and its magnetic penetration depth, as well as for wire and via inductances, and for via critical currents. The uniformity of the junction critical current Icacross a wafer was measured on test chips with 2.7-μm-diameter junctions. Within a 5 mm × 5 mm area, the standard deviation of Icwas ~2% for chips near the center of the wafer and up to ~7% for chips near the edge. We also describe process improvements and innovations under development aimed at increasing circuit density and high-speed performance.
To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.
Superconducting digital circuits based on Josephson junctions with amorphous niobium-silicon (a-NbSi) barriers have been designed, fabricated, and tested. Single-flux-quantum (SFQ) shift registers operated with ±30% bias margins, confirming junction reproducibility and uniformity. Static digital dividers operated up to 165 GHz for a single value of bias current, which was only marginally slower than circuits fabricated with externally shunted AlOx-barrier junctions having a comparable critical current density of 4.5 kA/cm2. In comparison, self-shunted a-NbSi junctions enabled a doubling in circuit density. This and their relatively thick 10 nm barriers could increase the yield of complex SFQ circuits.
Abstract We report on the electrical properties of NbN/TaN/NbN Josephson junctions grown on thermally oxidized silicon substrates, along with the design and fabrication of superconducting single-flux-quantum (SFQ) circuits based on these NbN superconductor/normal metal/superconductor (SNS) junctions. The critical current density ( J c ) of the junctions was found to be relatively sensitive to the barrier thickness, decreasing from 108.0 ± 8.1 kA cm −2 for a 15 nm barrier to 12.8 ± 1.9 kA cm −2 for a 30 nm barrier. For a J c of approximately 24.5 ± 2.1 kA cm −2 and a barrier thickness of 25 nm, the NbN SNS junctions are self-shunted and exhibit nonhysteretic current–voltage ( I – V ) characteristics. Especially for junctions with diameter ( φ ) ranging from 0.8 to 1.6 μ m, their critical current ( I c ) falls within the range of 110–450 μ A, making them suitable for SFQ circuits. By considering the impact of excess current and incorporating it as an additional term in the conventional resistively and capacitively shunted junction model, the I – V curves of NbN SNS junctions can be precisely described, successfully minimizing the deviation between simulations and test results. The DC-SFQ and SFQ-DC interface circuits can both operate normally, and the bias margins of cell circuits such as Josephson transmission line, confluence buffer, D flip-flop, and splitter are greater than 40%. Compared to Nb superconductor/insulator/superconductor junctions, their self-shunting characteristics and relatively thick 25 nm barriers can also enhance the integration of circuits and increase the yield to complex circuits.
To increase the integration scale of superconductor electronics, we are developing a new node, titled SFQ7ee, of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized superconducting layers to ten and utilized NbN and NbN/Nb kinetic inductors to increase the possible inductor number density above a hundred million inductors per cm2. Increasing the Josephson junction number density to the same level requires implementing self-shunted high-JcJosephson junctions. We investigated the properties of Nb/NbNx/Nb trilayer junctions as a potential replacement of high-JcNb/Al-AlOx/Nb junctions, where NbNxis a disordered, overstoichiometric, nonsuperconducting nitride deposited by reactive sputtering. Dependences of theIcRnproduct and Josephson critical current density, Jc on the NbNx barrier thickness and temperature were studied in the thickness range from 5 nm to 20 nm. The fabricated junctions can be well described by the microscopic theory of SNS junctions, assuming no suppression of the energy gap in Nb electrodes near the NbNxinterfaces and a Cooper pair decay length in the NbNx barrier, ξnTcof about 2.3 nm. Current-voltage characteristics of the junctions are well described by the resistively and capacitively shunted junction (RCSJ) model without excess current. In the studied rangeJc2, the Nb/NbNx/Nb junctions have lower values of the specific resistanceRnA, lower IcRn products, and a stronger dependence of theIcRnon temperature than the self-shunted or critically damped externally shunted Nb/Al-AlOx/Nb junctions with the same critical current density; A is the junction area,Icthe junction critical current, and Rnthe effective shunting resistance.
Development of 15kA/cm2^22 Fabrication Process for Superconducting Integrated Digital Circuits
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 ΩΩΩ, followed by the deposition of Nb/Al-AlOx_xx​/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm2^22. To increase the Al-AlOx_xx​ barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.
We have demonstrated a new planarized all-refractory technology for low Tc superconductivity (PARTS). With the exception of the Nb-AlOx-Nb trilayer preparation, the processing is done almost exclusively within an advanced Si technology fabrication facility. This approach has allowed us to leverage highly off of existing state-of-the-art lithography, metal etching, materials deposition, and planarization capabilities. Using chemical-mechanical polish as the planarization technique we have fabricated Josephson junctions ranging in size from 0.5–100 μm2. Junction quality is excellent with the figure of merit Vm typically exceeding 70 mV. PARTS has yielded fully functional integrated Josephson devices including magnetometers, gradiometers, and soliton oscillators.