Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Superconductor Science and Technology

Nanoscale NbN/TaN/NbN Josephson junctions for superconducting memory cells

Zengxu Zheng, Lu Zhang, Y X Hu, Yulong Zhong, J J Xie, X Y Liu, Weifeng Shi, Huiwu Wang, Wei Peng, Lei Chen, Zhen Wang

Published Sep 1, 2025• 1 citation
Publisher

Abstract

Abstract Superconducting flux memory devices fabricated with nanoscale junctions and high-inductance materials can maintain high-speed access performance while significantly reducing the area required for superconducting loops. In this work, we present a method for preparing nanoscale NbN-based superconductor/normal-metal/superconductor (SNS) Josephson junctions that combines electron beam lithography with chemical mechanical planarization process. Scanning electron microscope images reveal that the junction has a very round shape, while cross-sectional transmission electron microscopy shows that it has a truncated cone structure, characterized by a narrow top and a wide bottom. The minimum diameter of the junction is 51 nm, with the diameter at the interface between the wiring layer and the top electrode being just 27 nm. These nanoscale junctions exhibit excellent Josephson properties with a critical current density J c of 673 ± 64 kA cm −2 and a characteristic voltage V c of 1.63 ± 0.45 mV at 4.2 K. Furthermore, we designed the superconducting memory cell based on the simulated inductance values of the NbN loop and the nanoscale NbN-based SNS junctions. The cell has a total area of 12.6 μ m × 6.5 μ m and contains a radio-frequency superconducting quantum interference device with one junction in the storage loop and a direct-current superconducting quantum interference device with two junctions in the readout loop. Using the flux-locked and feedback measurement method, a clear flux hysteresis curve can be obtained to verify the read-write functions of the device.

DOI
10.1088/1361-6668/ae06cc

Related papers

Intrinsically shunted NbN/TaN/NbN Josephson junctions on Si substrates for large-scale integrated circuits applications

Kaixin Yan, Lu Zhang, Yulong Zhong +8 more

Abstract Superconducting circuits based on Josephson junctions have the potential to achieve high speed and ultra-low power consumption, but their integration is limited by the low controllability of Nb-based tunnel junction and the existence of shunt resistors. In this work, we report the fabrication of superconductor/normal metal/superconductor (SNS) Josephson junctions with high reproducibility on oxidized Si substrates. The junctions based on NbN/TaN/NbN trilayers measured at 4.2 K show excellent Josephson properties with a wide range of critical current ( I c ) from 227 to 2000 μ A. The variations of critical current density ( J c ) and characteristic voltage ( V c ) are respectively less than 7.1% and 7.5% in the 2 inch region. The standard deviation of I c is calculated to be less than 1.7% for Josephson arrays with the number of junctions up to 10 000 occupying an area of 0.34 mm 2 . The results provide a guarantee for the applications of NbN-SNS Josephson junctions in superconducting large-scale integrated circuits.

Superconductor Science and Technology•Feb 28, 2022•7 citations

Nonvolatile memory cell using a superconducting-ferromagnetic π Josephson junction

Junwen Zeng, Lei Chen, Xianghai Zhong +8 more

Abstract Storage of a single magnetic flux quantum in a superconducting loop containing a Josephson junction represents a promising unit cell configuration for construction of a cryogenic memory of superconducting digital circuits. However, application of a DC bias current is required for operation of such a memory cell to maintain trapping of the flux quantum in the storage loop. In this work, we present a superconducting memory cell that uses a superconducting-magnetic π junction. The cell characteristics show flux quantum hysteresis centering at the zero-bias current. We develop a fabrication process that combines superconductor–ferromagnet–superconductor (SFS) junctions with superconductor–normal metal–superconductor (SNS) junctions. The critical current density of the SFS junctions shows a 0–π oscillation as a function of the ferromagnetic layer thickness. The formation of the π junction is confirmed further by the flux modulation curves of a superconducting quantum interference device made from SNS junctions with an additional SFS junction.

Superconductor Science and Technology•Jul 13, 2022•9 citations

Fabrication and characterization of NbN/(TaN/NbN) N stacked Josephson junctions

Lu Zhang, Yuanhe Tao, Yulong Zhong +8 more

Abstract In this work, we present a detailed study of the electrical properties of stacked NbN/(TaN/NbN) N Josephson junctions. Cross-sectional scanning transmission electron microscopy analysis of the 5-stacked junction shows that the multilayer interface is very flat, each barrier has the same thickness, and the sidewalls of the junctions are nearly perpendicular to the substrate. Stacked junctions of different sizes and stacking numbers all have only one transition in their current–voltage curves. This indicates that the critical currents of the junctions in the stacked junctions are almost the same, showing the stability and repeatability of the multilayer fabrication and etching process. At 4.2 K, the 4-stacked junction shows excellent Josephson properties with characteristic voltage V c of 3.54 mV, which is about four times the 0.88 mV of the single junction. The temperature dependence of critical current density J c and V c of the stacked junction with N = 1, 2, 4 were measured, all of which can be fitted with dirty-limit theory. Stacked junctions with larger V c or more stacked layers can be achieved by optimizing electrode and barrier thickness, barrier resistivity, and thermal relaxation rate, etc.

Superconductor Science and Technology•Nov 2, 2022•3 citations

Single-flux-quantum circuits utilizing self-shunted NbN/TaN/NbN Josephson junctions grown on silicon substrates

Yulong Zhong, Lu Zhang, Junjie Xie +9 more

Abstract We report on the electrical properties of NbN/TaN/NbN Josephson junctions grown on thermally oxidized silicon substrates, along with the design and fabrication of superconducting single-flux-quantum (SFQ) circuits based on these NbN superconductor/normal metal/superconductor (SNS) junctions. The critical current density ( J c ) of the junctions was found to be relatively sensitive to the barrier thickness, decreasing from 108.0 ± 8.1 kA cm −2 for a 15 nm barrier to 12.8 ± 1.9 kA cm −2 for a 30 nm barrier. For a J c of approximately 24.5 ± 2.1 kA cm −2 and a barrier thickness of 25 nm, the NbN SNS junctions are self-shunted and exhibit nonhysteretic current–voltage ( I – V ) characteristics. Especially for junctions with diameter ( φ ) ranging from 0.8 to 1.6 μ m, their critical current ( I c ) falls within the range of 110–450 μ A, making them suitable for SFQ circuits. By considering the impact of excess current and incorporating it as an additional term in the conventional resistively and capacitively shunted junction model, the I – V curves of NbN SNS junctions can be precisely described, successfully minimizing the deviation between simulations and test results. The DC-SFQ and SFQ-DC interface circuits can both operate normally, and the bias margins of cell circuits such as Josephson transmission line, confluence buffer, D flip-flop, and splitter are greater than 40%. Compared to Nb superconductor/insulator/superconductor junctions, their self-shunting characteristics and relatively thick 25 nm barriers can also enhance the integration of circuits and increase the yield to complex circuits.

Superconductor Science and Technology•Oct 6, 2024•6 citations

Fabrication Process for Deep Submicron SQUID Circuits with Three Independent Niobium Layers

Silke Wolter, Julian Linek, Josepha Altmann +6 more

We present a fabrication technology for nanoscale superconducting quantum interference devices (SQUIDs) with overdamped superconductor-normal metal-superconductor (SNS) trilayer Nb/HfTi/Nb Josephson junctions. A combination of electron-beam lithography with chemical-mechanical polishing and magnetron sputtering on thermally oxidized Si wafers is used to produce direct current SQUIDs with 100-nm-lateral dimensions for Nb lines and junctions. We extended the process from originally two to three independent Nb layers. This extension offers the possibility to realize superconducting vias to all Nb layers without the HfTi barrier, and hence to increase the density and complexity of circuit structures. We present results on the yield of this process and measurements of SQUID characteristics.

Micromachines•Mar 24, 2021•3 citations

A compact superconducting nanowire memory element operated by nanowire cryotrons

Qingyuan Zhao, Emily Toomey, Brenden Butters +4 more

Abstract A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10 −19 J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μ m × 7 μ m in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.

arXiv:1711.08290•Superconductor Science and Technology•Jan 16, 2018•54 citations
Abstract Superconducting flux memory devices fabricated with nanoscale junctions and high-inductance materials can maintain high-speed access performance while significantly reducing the area required for superconducting loops. In this work, we present a method for preparing nanoscale NbN-based superconductor/normal-metal/superconductor (SNS) Josephson junctions that combines electron beam lithography with chemical mechanical planarization process. Scanning electron microscope images reveal that the junction has a very round shape, while cross-sectional transmission electron microscopy shows that it has a truncated cone structure, characterized by a narrow top and a wide bottom. The minimum diameter of the junction is 51 nm, with the diameter at the interface between the wiring layer and the top electrode being just 27 nm. These nanoscale junctions exhibit excellent Josephson properties with a critical current density J c of 673 ± 64 kA cm −2 and a characteristic voltage V c of 1.63 ± 0.45 mV at 4.2 K. Furthermore, we designed the superconducting memory cell based on the simulated inductance values of the NbN loop and the nanoscale NbN-based SNS junctions. The cell has a total area of 12.6 μ m × 6.5 μ m and contains a radio-frequency superconducting quantum interference device with one junction in the storage loop and a direct-current superconducting quantum interference device with two junctions in the readout loop. Using the flux-locked and feedback measurement method, a clear flux hysteresis curve can be obtained to verify the read-write functions of the device.
Abstract Superconducting circuits based on Josephson junctions have the potential to achieve high speed and ultra-low power consumption, but their integration is limited by the low controllability of Nb-based tunnel junction and the existence of shunt resistors. In this work, we report the fabrication of superconductor/normal metal/superconductor (SNS) Josephson junctions with high reproducibility on oxidized Si substrates. The junctions based on NbN/TaN/NbN trilayers measured at 4.2 K show excellent Josephson properties with a wide range of critical current ( I c ) from 227 to 2000 μ A. The variations of critical current density ( J c ) and characteristic voltage ( V c ) are respectively less than 7.1% and 7.5% in the 2 inch region. The standard deviation of I c is calculated to be less than 1.7% for Josephson arrays with the number of junctions up to 10 000 occupying an area of 0.34 mm 2 . The results provide a guarantee for the applications of NbN-SNS Josephson junctions in superconducting large-scale integrated circuits.
Abstract Storage of a single magnetic flux quantum in a superconducting loop containing a Josephson junction represents a promising unit cell configuration for construction of a cryogenic memory of superconducting digital circuits. However, application of a DC bias current is required for operation of such a memory cell to maintain trapping of the flux quantum in the storage loop. In this work, we present a superconducting memory cell that uses a superconducting-magnetic π junction. The cell characteristics show flux quantum hysteresis centering at the zero-bias current. We develop a fabrication process that combines superconductor–ferromagnet–superconductor (SFS) junctions with superconductor–normal metal–superconductor (SNS) junctions. The critical current density of the SFS junctions shows a 0–π oscillation as a function of the ferromagnetic layer thickness. The formation of the π junction is confirmed further by the flux modulation curves of a superconducting quantum interference device made from SNS junctions with an additional SFS junction.
Abstract In this work, we present a detailed study of the electrical properties of stacked NbN/(TaN/NbN) N Josephson junctions. Cross-sectional scanning transmission electron microscopy analysis of the 5-stacked junction shows that the multilayer interface is very flat, each barrier has the same thickness, and the sidewalls of the junctions are nearly perpendicular to the substrate. Stacked junctions of different sizes and stacking numbers all have only one transition in their current–voltage curves. This indicates that the critical currents of the junctions in the stacked junctions are almost the same, showing the stability and repeatability of the multilayer fabrication and etching process. At 4.2 K, the 4-stacked junction shows excellent Josephson properties with characteristic voltage V c of 3.54 mV, which is about four times the 0.88 mV of the single junction. The temperature dependence of critical current density J c and V c of the stacked junction with N = 1, 2, 4 were measured, all of which can be fitted with dirty-limit theory. Stacked junctions with larger V c or more stacked layers can be achieved by optimizing electrode and barrier thickness, barrier resistivity, and thermal relaxation rate, etc.
Abstract We report on the electrical properties of NbN/TaN/NbN Josephson junctions grown on thermally oxidized silicon substrates, along with the design and fabrication of superconducting single-flux-quantum (SFQ) circuits based on these NbN superconductor/normal metal/superconductor (SNS) junctions. The critical current density ( J c ) of the junctions was found to be relatively sensitive to the barrier thickness, decreasing from 108.0 ± 8.1 kA cm −2 for a 15 nm barrier to 12.8 ± 1.9 kA cm −2 for a 30 nm barrier. For a J c of approximately 24.5 ± 2.1 kA cm −2 and a barrier thickness of 25 nm, the NbN SNS junctions are self-shunted and exhibit nonhysteretic current–voltage ( I – V ) characteristics. Especially for junctions with diameter ( φ ) ranging from 0.8 to 1.6 μ m, their critical current ( I c ) falls within the range of 110–450 μ A, making them suitable for SFQ circuits. By considering the impact of excess current and incorporating it as an additional term in the conventional resistively and capacitively shunted junction model, the I – V curves of NbN SNS junctions can be precisely described, successfully minimizing the deviation between simulations and test results. The DC-SFQ and SFQ-DC interface circuits can both operate normally, and the bias margins of cell circuits such as Josephson transmission line, confluence buffer, D flip-flop, and splitter are greater than 40%. Compared to Nb superconductor/insulator/superconductor junctions, their self-shunting characteristics and relatively thick 25 nm barriers can also enhance the integration of circuits and increase the yield to complex circuits.
We present a fabrication technology for nanoscale superconducting quantum interference devices (SQUIDs) with overdamped superconductor-normal metal-superconductor (SNS) trilayer Nb/HfTi/Nb Josephson junctions. A combination of electron-beam lithography with chemical-mechanical polishing and magnetron sputtering on thermally oxidized Si wafers is used to produce direct current SQUIDs with 100-nm-lateral dimensions for Nb lines and junctions. We extended the process from originally two to three independent Nb layers. This extension offers the possibility to realize superconducting vias to all Nb layers without the HfTi barrier, and hence to increase the density and complexity of circuit structures. We present results on the yield of this process and measurements of SQUID characteristics.
Abstract A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10 −19 J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μ m × 7 μ m in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.