Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

Error rate measurements of a Josephson single flux quantum binary ripple counter

D.J. Durand, Robert D. Sandell, Lee O. Heflinger, Arnold H. Silver

Published Jun 1, 1992• 13 citations
Publisher

Abstract

Single-flux quantum devices are used in superconductive analog-to-digital converters (ADCs), shift registers, and memory cells. They have been proposed for logic applications. The authors report the performance of high-speed superconducting, single-flux quantum (SFQ) ripple counters. Both memory and logic functions of the counter are investigated. Errors in logic operation produce bit error rates (BERs) as low as 0.22 errors per million binary operations, measured while counting 100-MHz pseudorandom input pulses. Errors in memory function do not occur on the time scale of the measurements. The BER is shown to be nearly independent of input bit rate and pattern, but strongly dependent on the counter cell operating point.< >

DOI
10.1109/77.139227

Related papers

High speed non-latching SQUID binary ripple counter

Arnold H. Silver, R. Phillips, Robert D. Sandell

High speed, single flux quantum (SFQ) binary scalers are important components in superconducting analog-to-digital converters (ADC). This paper reviews the concept for a SQUID ADC and the design of an SFQ binary ripple counter, and reports the simulation of key components, and fabrication and performance of non-latching SQUID scalers and SFQ binary ripple counters. The SQUIDs were fabricated with Nb/Nb2O5/PbIn junctions and interconnected by monolithic-superconducting transmission lines and isolation resistors. Each SQUID functioned as a bistable flip-flop with the input connected to the center of the device and the output across one junction. All junctions were critically damped to optimize the pulse response. Operation was verified by observing the do I-V curves of successive SQUIDs driven by a cw pulse train generated on the same chip. Each SQUID exhibited constant-voltage current steps at 1/2 the voltage of the preceding device as expected from the Josephson voltage-to-frequency relation. Steps were observed only for the same voltage polarity of successive devices and for proper phase bias of the SQUID. Binary frequency division was recorded up to 40GHz for devices designed to operate to 28GHz.

IEEE Transactions on Magnetics•Mar 1, 1985•29 citations

Bit error rate measurements on RSFQ circuits using a SQUID current comparator

Masaaki Maezawa, Fuminori Hirayama, Motohiro Suzuki

We propose a simple method of measuring bit error rates (BERs) for rapid single flux quantum (RSFQ) circuits operating at high frequencies. An error detector based on a SQUID current comparator, which operates without a timing clock, is employed to simplify the test system and measurements. We successfully investigated high-frequency operation of RSFQ cells that were utilized to implement our RSFQ digital-to-analogue converter for metrology applications. Sufficiently low BERs were demonstrated in the circuit operation at several tens of gigahertz.

Superconductor Science and Technology•Mar 16, 2006•0 citations

Counting SFQ analog to digital converter results

Robert D. Sandell, D.J. Durand, Bruce J. Dalrymple +1 more

We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout (DRO). The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate (SRG) at the carry out of the counter, we have measured the bit error rates (BER) of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit counters connected to the two quantizer outputs were compared. We measured a BER of /spl sim/5/spl times/10/sup -11/ with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•0 citations

High-speed single flux-quantum up/down counter for neural computation using stochastic logic

Takeshi Onomi, Takaharu Kondo, Kiyotaka Nakajima

We propose the high-speed single flux-quantum(SFQ) up/down counter for the neural computation using stochastic logic. Up and down signals are counted by two independent counters, respectively. The proposed counter circuit can count SFQ signals of 50GHz with large operation margins. To realize the up/down counter, we fabricated a 2-bit up counter circuit and a 2-bit down counter circuit as basic blocks by Nb integrated circuits. The low-speed test results of these circuits show correct operations. We also measured dc voltages of Josephson transmission lines to investigate the responses of carry operations for SFQ pulse trains. The results show that the counter circuits have potential to count 144GHz SFQ pulses.

Journal of Physics Conference Series•Feb 1, 2008•7 citations

Experimental evaluation of some rapid single flux quantum cells

Ying Ki Kwong, V. Nandakumar

Some basic cells in the rapid single-flux quantum (RSFQ) family of superconductive logic circuits were studied. An input stage, a buffer, and an OR gate were simulated and laid out for a standard niobium-based fabrication process. The resulting circuits perform properly for clock speeds up to 1 GHz. For the simpler circuits tested, the measured margins are wide, consistent with simulations, and not very dependent on clock speed. However, margin decreases with increased circuit complexity. The input stage converts a rising edge into an SFQ pulse, which has a small amplitude and narrow width in time. On the present circuits, these pulses are about 200 mu V in amplitude and 10 ps in width. To facilitate measurement, the authors have chosen as the output an asymmetrical superconducting quantum interference device (SQUID) consisting of two Josephson junctions. It converts SFQ pulses into 2.5 mV latching output levels on chip. By inductively coupling SFQ pulses into the SQUID loop, DC current isolation between the RSFQ circuit-under-test and the output stage is provided. The SQUID was optimized for 2 GHz operations.>

IEEE Transactions on Applied Superconductivity•Mar 1, 1993•7 citations

Prospect of single flux quantum logic in superconducting digital electronics

J.H. Kang, John X. Przybysz, Donald L. Miller +2 more

This paper presents a study on the merits of single flux quantum (SFQ) logic in superconducting digital electronics. With no requirements for an external RF clock source, the speed of SFQ logic circuits can exceed 100 GHz, orders of magnitude higher than latching logic circuits. Use of overdamped junctions in SFQ circuits makes this logic available for already developed high-Tc junctions. Simulations show the operation of SFQ circuits at above 10 GHz with the junctions having characteristics similar to those of YBa2Cu3O7-x/Au/YBa2Cu3O7-x planar junctions. A similar concept is applied to NbN circuits operable above 10 K. A flip-flop counter using NbN junctions with Vm (1.5 mV)=3 mV and Delta =1.9 mV to model 12 K operation has been successfully simulated up to 5 GHz. Operating margins of only 26% on MVTL shift register were obtained by simulations, which is comparable to the margins for SFQ logic circuits. A counting SFQ analogue-to-digital converter can be improved by using an output buffered quantizer.

Superconductor Science and Technology•Nov 1, 1991•5 citations
Single-flux quantum devices are used in superconductive analog-to-digital converters (ADCs), shift registers, and memory cells. They have been proposed for logic applications. The authors report the performance of high-speed superconducting, single-flux quantum (SFQ) ripple counters. Both memory and logic functions of the counter are investigated. Errors in logic operation produce bit error rates (BERs) as low as 0.22 errors per million binary operations, measured while counting 100-MHz pseudorandom input pulses. Errors in memory function do not occur on the time scale of the measurements. The BER is shown to be nearly independent of input bit rate and pattern, but strongly dependent on the counter cell operating point.< >
High speed, single flux quantum (SFQ) binary scalers are important components in superconducting analog-to-digital converters (ADC). This paper reviews the concept for a SQUID ADC and the design of an SFQ binary ripple counter, and reports the simulation of key components, and fabrication and performance of non-latching SQUID scalers and SFQ binary ripple counters. The SQUIDs were fabricated with Nb/Nb2O5/PbIn junctions and interconnected by monolithic-superconducting transmission lines and isolation resistors. Each SQUID functioned as a bistable flip-flop with the input connected to the center of the device and the output across one junction. All junctions were critically damped to optimize the pulse response. Operation was verified by observing the do I-V curves of successive SQUIDs driven by a cw pulse train generated on the same chip. Each SQUID exhibited constant-voltage current steps at 1/2 the voltage of the preceding device as expected from the Josephson voltage-to-frequency relation. Steps were observed only for the same voltage polarity of successive devices and for proper phase bias of the SQUID. Binary frequency division was recorded up to 40GHz for devices designed to operate to 28GHz.
We propose a simple method of measuring bit error rates (BERs) for rapid single flux quantum (RSFQ) circuits operating at high frequencies. An error detector based on a SQUID current comparator, which operates without a timing clock, is employed to simplify the test system and measurements. We successfully investigated high-frequency operation of RSFQ cells that were utilized to implement our RSFQ digital-to-analogue converter for metrology applications. Sufficiently low BERs were demonstrated in the circuit operation at several tens of gigahertz.
We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout (DRO). The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate (SRG) at the carry out of the counter, we have measured the bit error rates (BER) of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit counters connected to the two quantizer outputs were compared. We measured a BER of /spl sim/5/spl times/10/sup -11/ with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.
We propose the high-speed single flux-quantum(SFQ) up/down counter for the neural computation using stochastic logic. Up and down signals are counted by two independent counters, respectively. The proposed counter circuit can count SFQ signals of 50GHz with large operation margins. To realize the up/down counter, we fabricated a 2-bit up counter circuit and a 2-bit down counter circuit as basic blocks by Nb integrated circuits. The low-speed test results of these circuits show correct operations. We also measured dc voltages of Josephson transmission lines to investigate the responses of carry operations for SFQ pulse trains. The results show that the counter circuits have potential to count 144GHz SFQ pulses.
Some basic cells in the rapid single-flux quantum (RSFQ) family of superconductive logic circuits were studied. An input stage, a buffer, and an OR gate were simulated and laid out for a standard niobium-based fabrication process. The resulting circuits perform properly for clock speeds up to 1 GHz. For the simpler circuits tested, the measured margins are wide, consistent with simulations, and not very dependent on clock speed. However, margin decreases with increased circuit complexity. The input stage converts a rising edge into an SFQ pulse, which has a small amplitude and narrow width in time. On the present circuits, these pulses are about 200 mu V in amplitude and 10 ps in width. To facilitate measurement, the authors have chosen as the output an asymmetrical superconducting quantum interference device (SQUID) consisting of two Josephson junctions. It converts SFQ pulses into 2.5 mV latching output levels on chip. By inductively coupling SFQ pulses into the SQUID loop, DC current isolation between the RSFQ circuit-under-test and the output stage is provided. The SQUID was optimized for 2 GHz operations.>
This paper presents a study on the merits of single flux quantum (SFQ) logic in superconducting digital electronics. With no requirements for an external RF clock source, the speed of SFQ logic circuits can exceed 100 GHz, orders of magnitude higher than latching logic circuits. Use of overdamped junctions in SFQ circuits makes this logic available for already developed high-Tc junctions. Simulations show the operation of SFQ circuits at above 10 GHz with the junctions having characteristics similar to those of YBa2Cu3O7-x/Au/YBa2Cu3O7-x planar junctions. A similar concept is applied to NbN circuits operable above 10 K. A flip-flop counter using NbN junctions with Vm (1.5 mV)=3 mV and Delta =1.9 mV to model 12 K operation has been successfully simulated up to 5 GHz. Operating margins of only 26% on MVTL shift register were obtained by simulations, which is comparable to the margins for SFQ logic circuits. A counting SFQ analogue-to-digital converter can be improved by using an output buffered quantizer.